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authorYann Herklotz <git@yannherklotz.com>2020-07-05 02:46:11 +0100
committerYann Herklotz <git@yannherklotz.com>2020-07-05 02:46:11 +0100
commitd6c6c87d61dc10b1acaeb056975675c7e523f1ef (patch)
tree9b21d35d5de8606a231c83a1de75c0586410642a /src/translation/Veriloggenproof.v
parent322f3a1c2d547490b0e92a8f1ef937e1d68c2a6b (diff)
downloadvericert-d6c6c87d61dc10b1acaeb056975675c7e523f1ef.tar.gz
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Remove admitted in mis_stepp_Vdecl
Diffstat (limited to 'src/translation/Veriloggenproof.v')
-rw-r--r--src/translation/Veriloggenproof.v8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/translation/Veriloggenproof.v b/src/translation/Veriloggenproof.v
index 3052d03..ee0aa64 100644
--- a/src/translation/Veriloggenproof.v
+++ b/src/translation/Veriloggenproof.v
@@ -195,8 +195,12 @@ Section CORRECTNESS.
Lemma mis_stepp_decl :
forall l asr asa f,
- mis_stepp f asr asa l asr asa.
- Admitted.
+ mis_stepp f asr asa (map Vdeclaration l) asr asa.
+ Proof.
+ induction l.
+ - intros. constructor.
+ - intros. simplify. econstructor. constructor. auto.
+ Qed.
Let ge : HTL.genv := Globalenvs.Genv.globalenv prog.
Let tge : genv := Globalenvs.Genv.globalenv tprog.