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author | James Pollard <james@pollard.dev> | 2020-06-12 17:55:00 +0100 |
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committer | James Pollard <james@pollard.dev> | 2020-06-12 17:55:00 +0100 |
commit | a01219884ec78f6c32ed98b31587a66278e0cddc (patch) | |
tree | bb588daab3bade6b88b611bf720d78060de0673d /src/translation | |
parent | f7795011ea9ac0d34ee565d3832f15b649bf1827 (diff) | |
parent | 5f70d1627fb6d60a91dc2e93058c56e6d5c98ec2 (diff) | |
download | vericert-a01219884ec78f6c32ed98b31587a66278e0cddc.tar.gz vericert-a01219884ec78f6c32ed98b31587a66278e0cddc.zip |
Merge branch 'master' into arrays-proof
Diffstat (limited to 'src/translation')
-rw-r--r-- | src/translation/HTLgen.v | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/translation/HTLgen.v b/src/translation/HTLgen.v index c73aaa7..d35a296 100644 --- a/src/translation/HTLgen.v +++ b/src/translation/HTLgen.v @@ -256,8 +256,7 @@ Definition translate_eff_addressing (a: Op.addressing) (args: list reg) : mon ex (* Stack arrays/referenced variables *) | Op.Ainstack a, nil => (* We need to be sure that the base address is aligned *) let a := Integers.Ptrofs.unsigned a in (* FIXME: Assuming stack offsets are +ve; is this ok? *) - if (Z.eq_dec (Z.modulo a 4) 0) then ret (Vlit (ZToValue 32 (a / 4))) - else error (Errors.msg "Veriloggen: eff_addressing misaligned stack offset") + ret (Vlit (ZToValue 32 a)) | _, _ => error (Errors.msg "Veriloggen: eff_addressing instruction not implemented: other") end. @@ -336,14 +335,17 @@ Definition add_branch_instr (e: expr) (n n1 n2: node) : mon unit := Definition translate_arr_access (mem : AST.memory_chunk) (addr : Op.addressing) (args : list reg) (stack : reg) : mon expr := match mem, addr, args with (* TODO: We should be more methodical here; what are the possibilities?*) - | Mint32, Op.Aindexed off, r1::nil => ret (Vvari stack (boplitz Vadd r1 off)) (* FIXME: Cannot guarantee alignment *) + | Mint32, Op.Aindexed off, r1::nil => (* FIXME: Cannot guarantee alignment *) + ret (Vvari stack (Vbinop Vadd (boplitz Vdiv r1 4) (Vlit (ZToValue 32 (off / 4))))) | Mint32, Op.Ascaled scale offset, r1::nil => if ((Z.eqb (Z.modulo scale 4) 0) && (Z.eqb (Z.modulo offset 4) 0)) then ret (Vvari stack (Vbinop Vadd (boplitz Vmul r1 (scale / 4)) (Vlit (ZToValue 32 (offset / 4))))) else error (Errors.msg "Veriloggen: translate_arr_access address misaligned") | Mint32, Op.Aindexed2scaled scale offset, r1::r2::nil => (* Typical for dynamic array addressing *) if ((Z.eqb (Z.modulo scale 4) 0) && (Z.eqb (Z.modulo offset 4) 0)) - then ret (Vvari stack (Vbinop Vadd (boplitz Vadd r1 (offset / 4)) (boplitz Vmul r2 (scale / 4)))) + then ret (Vvari stack + (Vbinop Vadd (Vbinop Vadd (boplitz Vdiv r1 4) (Vlit (ZToValue 32 (offset / 4)))) + (boplitz Vmul r2 (scale / 4)))) else error (Errors.msg "Veriloggen: translate_arr_access address misaligned") | Mint32, Op.Ainstack a, nil => (* We need to be sure that the base address is aligned *) let a := Integers.Ptrofs.unsigned a in (* FIXME: Assuming stack offsets are +ve; is this ok? *) |