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author | Yann Herklotz <git@yannherklotz.com> | 2020-06-25 18:04:49 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-25 18:04:49 +0100 |
commit | cf9949a5151aa9ed86554fb31c2a56fad0614a10 (patch) | |
tree | 67928ef6df9af2eead81eb0b4f67ca92e0b8cdb0 /src/verilog/HTL.v | |
parent | 445aabbcf63e29d68dd0c98dde7f259af0381591 (diff) | |
download | vericert-cf9949a5151aa9ed86554fb31c2a56fad0614a10.tar.gz vericert-cf9949a5151aa9ed86554fb31c2a56fad0614a10.zip |
Progress on proof of Veriloggen
Diffstat (limited to 'src/verilog/HTL.v')
-rw-r--r-- | src/verilog/HTL.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index 0bf5072..a3623f0 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -99,12 +99,14 @@ Inductive state : Type := Inductive step : genv -> state -> Events.trace -> state -> Prop := | step_module : - forall g m st sf ctrl data + forall g m st sf ctrl data ist asr asa basr1 basa1 nasr1 nasa1 basr2 basa2 nasr2 nasa2 asr' asa' f stval pstval, + asr!(m.(mod_st)) = Some ist -> + valueToPos ist = st -> m.(mod_controllogic)!st = Some ctrl -> m.(mod_datapath)!st = Some data -> Verilog.stmnt_runp f |