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authorYann Herklotz <git@yannherklotz.com>2020-04-22 00:11:40 +0100
committerYann Herklotz <git@yannherklotz.com>2020-04-22 00:11:47 +0100
commit46d76082ae7039832f597f73720f701a866261a4 (patch)
tree7585a0dba411028345a64ee76a292eeec2849338 /src/verilog/PrintVerilog.mli
parentd4b07f44d83a73311096cd1b0bf99fe4227713b2 (diff)
downloadvericert-46d76082ae7039832f597f73720f701a866261a4.tar.gz
vericert-46d76082ae7039832f597f73720f701a866261a4.zip
Improve printing of results
Diffstat (limited to 'src/verilog/PrintVerilog.mli')
-rw-r--r--src/verilog/PrintVerilog.mli4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli
index b4d2937..c9fca8e 100644
--- a/src/verilog/PrintVerilog.mli
+++ b/src/verilog/PrintVerilog.mli
@@ -16,6 +16,8 @@
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*)
+val print_value : out_channel -> Value.value -> unit
+
val print_program : out_channel -> Verilog.coq_module -> unit
-val print_result : (BinNums.positive * Value.value) list -> unit
+val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit