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| author | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
|---|---|---|
| committer | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
| commit | f7795011ea9ac0d34ee565d3832f15b649bf1827 (patch) | |
| tree | fd731b58626c8665032afd62068ece8cedc76eb0 /src/verilog/PrintVerilog.mli | |
| parent | 9acb804500b590edbff66cd802216f58dde169cd (diff) | |
| parent | 86f42b92d87020875e2a7ef4ba40de12d261685f (diff) | |
| download | vericert-f7795011ea9ac0d34ee565d3832f15b649bf1827.tar.gz vericert-f7795011ea9ac0d34ee565d3832f15b649bf1827.zip | |
Merge branch 'master' into arrays-proof
Diffstat (limited to 'src/verilog/PrintVerilog.mli')
| -rw-r--r-- | src/verilog/PrintVerilog.mli | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index c9fca8e..0df9d06 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -18,6 +18,6 @@ val print_value : out_channel -> Value.value -> unit -val print_program : out_channel -> Verilog.coq_module -> unit +val print_program : out_channel -> Verilog.program -> unit val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit |