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| author | Michalis Pardalos <m.pardalos@gmail.com> | 2020-11-20 16:40:08 +0000 |
|---|---|---|
| committer | Michalis Pardalos <m.pardalos@gmail.com> | 2020-11-20 19:21:43 +0000 |
| commit | 9b87637d3e4d6a75dee1221b017e3ccf6632642e (patch) | |
| tree | a4c1ea2cb059d8d3ccb4c384c64e9633b76dad6e /src/verilog/PrintVerilog.mli | |
| parent | d79dae026b150e9671e0aa7262f6aa2d1d302502 (diff) | |
| download | vericert-9b87637d3e4d6a75dee1221b017e3ccf6632642e.tar.gz vericert-9b87637d3e4d6a75dee1221b017e3ccf6632642e.zip | |
Print instantiations in HTL output
Diffstat (limited to 'src/verilog/PrintVerilog.mli')
| -rw-r--r-- | src/verilog/PrintVerilog.mli | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 6a15ee9..1a37126 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -18,6 +18,8 @@ val pprint_stmnt : int -> Verilog.stmnt -> string +val pprint_instantiation : Verilog.instantiation -> string + val print_value : out_channel -> ValueInt.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit |