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| author | James Pollard <james@pollard.dev> | 2020-06-02 21:07:54 +0100 |
|---|---|---|
| committer | James Pollard <james@pollard.dev> | 2020-06-02 21:07:54 +0100 |
| commit | 7169b7666ad0577b5fadc1b0871a41ee7b124e82 (patch) | |
| tree | c6f54d0ddd6c1f991d6c41378bd987f4c4cdef51 /src/verilog/Verilog.v | |
| parent | 6d11e8674a3bf910d0df6600e8db9e8748844cf0 (diff) | |
| download | vericert-7169b7666ad0577b5fadc1b0871a41ee7b124e82.tar.gz vericert-7169b7666ad0577b5fadc1b0871a41ee7b124e82.zip | |
Update HTL semantics to support arrays.
Diffstat (limited to 'src/verilog/Verilog.v')
| -rw-r--r-- | src/verilog/Verilog.v | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index 2904d39..74c08fe 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -662,14 +662,16 @@ Definition genv := Genv.t unit unit. Inductive step : state -> state -> Prop := | step_module : - forall m stvar stvar' cycle f asr0 asa0 asr1 asa1, + forall m stvar stvar' cycle f + asr0 asa0 asr1 asa1 + asr' asa', mis_stepp (f cycle) asr0 asa0 m.(mod_body) asr1 asa1 -> - let asr := merge_associations asr1 in - let asa := merge_associations asa1 in - Some stvar' = asr.(assoc_blocking)!(fst m.(mod_state)) -> + asr' = merge_associations asr1 -> + asa' = merge_associations asa1 -> + Some stvar' = asr'.(assoc_blocking)!(fst m.(mod_state)) -> step (State m asr0 asa0 f cycle stvar) - (State m asr asa f (S cycle) stvar') + (State m asr' asa' f (S cycle) stvar') | step_finish : forall m asr asa f cycle stvar result, asr.(assoc_blocking)!(fst m.(mod_finish)) = Some (1'h"1") -> |