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| author | Yann Herklotz <git@yannherklotz.com> | 2020-07-07 13:50:55 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2020-07-07 13:50:55 +0100 |
| commit | fcb129725a68a052a079f882396be8e28142e1e0 (patch) | |
| tree | 6bf1a5380772071b3e5e23ac26e419d0f9ee779c /src/verilog/Verilog.v | |
| parent | 855ca59a303efd32f1979f4e508edb4ddb43adac (diff) | |
| download | vericert-fcb129725a68a052a079f882396be8e28142e1e0.tar.gz vericert-fcb129725a68a052a079f882396be8e28142e1e0.zip | |
Only translate_cond left
Diffstat (limited to 'src/verilog/Verilog.v')
| -rw-r--r-- | src/verilog/Verilog.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index 78b057d..43df3dd 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -143,7 +143,8 @@ Inductive binop : Type := | Vxor : binop (** xor (binary [^|]) *) | Vshl : binop (** shift left ([<<]) *) | Vshr : binop (** shift right ([>>>]) *) -| Vshru : binop. (** shift right unsigned ([>>]) *) +| Vshru : binop (** shift right unsigned ([>>]) *) +| Vror : binop. (** shift right unsigned ([>>]) *) (** ** Unary Operators *) @@ -324,6 +325,7 @@ Definition binop_run (op : binop) (v1 v2 : value) : option value := | Vshl => Some (Int.shl v1 v2) | Vshr => Some (Int.shr v1 v2) | Vshru => Some (Int.shru v1 v2) + | Vror => Some (Int.ror v1 v2) end. Definition unop_run (op : unop) (v1 : value) : value := |