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| author | Yann Herklotz <git@yannherklotz.com> | 2020-06-12 11:38:14 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-12 11:38:14 +0100 |
| commit | 7ad63f341fe3c28ef20bfde755bdf21403077504 (patch) | |
| tree | 88e57998e5ffaec6727baf99eff9fb0c5220d375 /src/verilog | |
| parent | 13b880f99b7355010551ad1b93242cf7773aa202 (diff) | |
| download | vericert-7ad63f341fe3c28ef20bfde755bdf21403077504.tar.gz vericert-7ad63f341fe3c28ef20bfde755bdf21403077504.zip | |
Remove Verilog proofs
Diffstat (limited to 'src/verilog')
| -rw-r--r-- | src/verilog/HTL.v | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index 2e4ef1a..c07d672 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -47,7 +47,12 @@ Record module: Type := mod_st : reg; mod_stk : reg; mod_finish : reg; - mod_return : reg + mod_return : reg; + mod_start : reg; + mod_reset : reg; + mod_clk : reg; + mod_scldecls : AssocMap.t (option Verilog.io * Verilog.scl_decl); + mod_arrdecls : AssocMap.t (option Verilog.io * Verilog.arr_decl); }. Definition fundef := AST.fundef module. |