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| author | Yann Herklotz <git@yannherklotz.com> | 2020-03-29 22:36:50 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-03-29 22:36:50 +0100 |
| commit | b298df2ab17f82e7ee113d9570df0a82fda53b17 (patch) | |
| tree | 03a16b453310a389acf5bbf4b8bc2c64399cbbf1 /src | |
| parent | ebb88fb0644280f7b39ce509b012fd26894feb23 (diff) | |
| download | vericert-b298df2ab17f82e7ee113d9570df0a82fda53b17.tar.gz vericert-b298df2ab17f82e7ee113d9570df0a82fda53b17.zip | |
Rename to transf_program
Diffstat (limited to 'src')
| -rw-r--r-- | src/translation/Veriloggen.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/translation/Veriloggen.v b/src/translation/Veriloggen.v index dbf1c80..41e7359 100644 --- a/src/translation/Veriloggen.v +++ b/src/translation/Veriloggen.v @@ -211,7 +211,7 @@ Fixpoint main_module (main : ident) (flist : list (ident * AST.globdef moddecl u | nil => None end. -Definition transf_function (d : design) : Errors.res verilog := +Definition transf_program (d : design) : Errors.res verilog := match main_module d.(AST.prog_main) d.(AST.prog_defs) with | Some m => transf_module m | _ => Errors.Error (Errors.msg "Could not find main module") |