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| author | Yann Herklotz <git@yannherklotz.com> | 2020-06-30 19:52:59 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-30 19:52:59 +0100 |
| commit | f8ff27915f8c4d5fb6f31ec2a0a73f65cf604c43 (patch) | |
| tree | e1186fac9de9c83ba0d0d0bc43bb9ac0fe86ef26 /src | |
| parent | f26f3887d0b0ac286c317a5425a3a4781871cfc2 (diff) | |
| download | vericert-f8ff27915f8c4d5fb6f31ec2a0a73f65cf604c43.tar.gz vericert-f8ff27915f8c4d5fb6f31ec2a0a73f65cf604c43.zip | |
Add htl pretty printing
Diffstat (limited to 'src')
| -rw-r--r-- | src/Compiler.v | 2 | ||||
| -rw-r--r-- | src/CoqupClflags.ml | 1 | ||||
| -rw-r--r-- | src/extraction/Extraction.v | 1 | ||||
| -rw-r--r-- | src/verilog/PrintVerilog.ml | 2 | ||||
| -rw-r--r-- | src/verilog/PrintVerilog.mli | 2 |
5 files changed, 7 insertions, 1 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 98ef429..a34b359 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -51,6 +51,7 @@ From coqup Require HTLgen. Parameter print_RTL: Z -> RTL.program -> unit. +Parameter print_HTL: HTL.program -> unit. Definition print {A: Type} (printer: A -> unit) (prog: A) : A := let unused := printer prog in prog. @@ -79,6 +80,7 @@ Definition transf_backend (r : RTL.program) : res Verilog.program := @@@ Inlining.transf_program @@ print (print_RTL 1) @@@ HTLgen.transl_program + @@ print print_HTL @@ Veriloggen.transl_program. Definition transf_frontend (p: Csyntax.program) : res RTL.program := diff --git a/src/CoqupClflags.ml b/src/CoqupClflags.ml index 83dd31d..5b40ce6 100644 --- a/src/CoqupClflags.ml +++ b/src/CoqupClflags.ml @@ -3,3 +3,4 @@ let option_simulate = ref false let option_hls = ref true let option_debug_hls = ref false let option_initial = ref false +let option_dhtl = ref false diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index ba87af6..df21dc4 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -128,6 +128,7 @@ Extract Constant Compiler.print_Clight => "PrintClight.print_if". Extract Constant Compiler.print_Cminor => "PrintCminor.print_if". Extract Constant driver.Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_RTL => "PrintRTL.print_if". +Extract Constant Compiler.print_HTL => "PrintHTL.print_if". Extract Constant Compiler.print_LTL => "PrintLTL.print_if". Extract Constant Compiler.print_Mach => "PrintMach.print_if". Extract Constant Compiler.print => "fun (f: 'a -> unit) (x: 'a) -> f x; x". diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 6d10887..5265c97 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -78,7 +78,7 @@ let rec pprint_expr = function | Vvari (s, i) -> concat [register s; "["; pprint_expr i; "]"] | Vinputvar s -> register s | Vunop (u, e) -> concat ["("; unop u; pprint_expr e; ")"] - | Vbinop (op, a, b) -> concat ["("; pprint_binop (pprint_expr a) (pprint_expr b) op; ")"] + | Vbinop (op, a, b) -> concat [pprint_binop (pprint_expr a) (pprint_expr b) op] | Vternary (c, t, f) -> concat ["("; pprint_expr c; " ? "; pprint_expr t; " : "; pprint_expr f; ")"] let rec pprint_stmnt i = diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 6544e52..62bf63f 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -16,6 +16,8 @@ * along with this program. If not, see <https://www.gnu.org/licenses/>. *) +val pprint_stmnt : int -> Verilog.stmnt -> string + val print_value : out_channel -> Value.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit |