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| author | Yann Herklotz <git@yannherklotz.com> | 2020-04-17 21:16:58 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2020-04-17 21:16:58 +0100 |
| commit | ef2fef6a290797f90c52a8a8706b7a5163cdb499 (patch) | |
| tree | b8010a89a19154e1d2e683e78dfe496288c96c33 /src | |
| parent | 7b383b469fa3ed0889fdbc4f3c5ee3ad3d89264b (diff) | |
| download | vericert-ef2fef6a290797f90c52a8a8706b7a5163cdb499.tar.gz vericert-ef2fef6a290797f90c52a8a8706b7a5163cdb499.zip | |
Fix Verilog.v
Diffstat (limited to 'src')
| -rw-r--r-- | src/verilog/Verilog.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index c1c68ba..61df580 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -419,7 +419,7 @@ Definition module_run (n : nat) (m : module) : res assoclist := Local Close Scope error_monad_scope. -Theorem value_eq_size_if_eq: +(*Theorem value_eq_size_if_eq: forall lv rv EQ, vsize lv = vsize rv -> value_eq_size lv rv = left EQ. Proof. intros. unfold value_eq_size. |