diff options
| -rw-r--r-- | driver/VericertDriver.ml | 4 | ||||
| -rw-r--r-- | src/Compiler.v | 6 | ||||
| -rw-r--r-- | src/VericertClflags.ml | 1 | ||||
| -rw-r--r-- | src/extraction/Extraction.v | 1 |
4 files changed, 11 insertions, 1 deletions
diff --git a/driver/VericertDriver.ml b/driver/VericertDriver.ml index 0362456..cb3ee8e 100644 --- a/driver/VericertDriver.ml +++ b/driver/VericertDriver.ml @@ -65,6 +65,7 @@ let compile_c_file sourcename ifile ofile = set_dest Vericert.PrintClight.destination option_dclight ".light.c"; set_dest Vericert.PrintCminor.destination option_dcminor ".cm"; set_dest Vericert.PrintRTL.destination option_drtl ".rtl"; + set_dest Vericert.PrintRTLBlock.destination option_drtlblock ".rtlblock"; set_dest Vericert.PrintHTL.destination option_dhtl ".htl"; set_dest Vericert.Regalloc.destination_alloctrace option_dalloctrace ".alloctrace"; set_dest Vericert.PrintLTL.destination option_dltl ".ltl"; @@ -254,6 +255,7 @@ Code generation options: (use -fno-<opt> to turn off -f<opt>) -dclight Save generated Clight in <file>.light.c -dcminor Save generated Cminor in <file>.cm -drtl Save RTL at various optimization points in <file>.rtl.<n> + -drtlblock Save RTLBlock <file>.rtlblock -dhtl Save HTL before Verilog generation <file>.htl -dltl Save LTL after register allocation in <file>.ltl -dmach Save generated Mach code in <file>.mach @@ -379,6 +381,7 @@ let cmdline_actions = Exact "-dclight", Set option_dclight; Exact "-dcminor", Set option_dcminor; Exact "-drtl", Set option_drtl; + Exact "-drtlblock", Set option_drtlblock; Exact "-dhtl", Set option_dhtl; Exact "-dltl", Set option_dltl; Exact "-dalloctrace", Set option_dalloctrace; @@ -391,6 +394,7 @@ let cmdline_actions = option_dclight := true; option_dcminor := true; option_drtl := true; + option_drtlblock := true; option_dhtl := true; option_dltl := true; option_dalloctrace := true; diff --git a/src/Compiler.v b/src/Compiler.v index cceb87d..ac5c664 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -60,6 +60,7 @@ From compcert Require Import Smallstep. Parameter print_RTL: Z -> RTL.program -> unit. Parameter print_HTL: HTL.program -> unit. +Parameter print_RTLBlock: RTLBlock.program -> unit. Definition print {A: Type} (printer: A -> unit) (prog: A) : A := let unused := printer prog in prog. @@ -110,9 +111,12 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := @@@ Cminorgen.transl_program @@@ Selection.sel_program @@@ RTLgen.transl_program - @@ Renumber.transf_program + @@@ Inlining.transf_program @@ print (print_RTL 0) + @@ Renumber.transf_program + @@ print (print_RTL 1) @@@ RTLBlockgen.transl_program + @@ print print_RTLBlock @@@ HTLSchedulegen.transl_program @@ print print_HTL @@ Veriloggen.transl_program. diff --git a/src/VericertClflags.ml b/src/VericertClflags.ml index ca591de..cbee31b 100644 --- a/src/VericertClflags.ml +++ b/src/VericertClflags.ml @@ -4,3 +4,4 @@ let option_hls = ref true let option_debug_hls = ref false let option_initial = ref false let option_dhtl = ref false +let option_drtlblock = ref false diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index f7131b0..d5cb9d7 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -134,6 +134,7 @@ Extract Constant Compiler.print_Clight => "PrintClight.print_if". Extract Constant Compiler.print_Cminor => "PrintCminor.print_if". Extract Constant driver.Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_RTL => "PrintRTL.print_if". +Extract Constant Compiler.print_RTLBlock => "PrintRTLBlock.print_if". Extract Constant Compiler.print_HTL => "PrintHTL.print_if". Extract Constant Compiler.print_LTL => "PrintLTL.print_if". Extract Constant Compiler.print_Mach => "PrintMach.print_if". |