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-rw-r--r--src/extraction/Extraction.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v
index 0028fcb..ba87af6 100644
--- a/src/extraction/Extraction.v
+++ b/src/extraction/Extraction.v
@@ -16,7 +16,7 @@
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*)
-From coqup Require Verilog Value Compiler Simulator.
+From coqup Require Verilog Value Compiler.
From Coq Require DecidableClass.
@@ -166,7 +166,7 @@ Set Extraction AccessOpaque.
Cd "src/extraction".
Separate Extraction
- Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls Simulator.simulate
+ Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls
Compiler.transf_c_program Compiler.transf_cminor_program
Cexec.do_initial_state Cexec.do_step Cexec.at_final_state