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-rw-r--r--src/Compiler.v5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/Compiler.v b/src/Compiler.v
index 7df00d8..5895e1d 100644
--- a/src/Compiler.v
+++ b/src/Compiler.v
@@ -74,7 +74,8 @@ From vericert Require
HTLgen
RTLBlock
RTLBlockgen
- HTLSchedulegen.
+ HTLSchedulegen
+ Pipeline.
From compcert Require Import Smallstep.
@@ -240,6 +241,8 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program :=
@@ print (print_RTL 6)
@@@ time "Unused globals" Unusedglob.transform_program
@@ print (print_RTL 7)
+ @@ Pipeline.transf_program
+ @@ print (print_RTL 8)
@@@ RTLBlockgen.transl_program
@@ print print_RTLBlock
@@@ HTLSchedulegen.transl_program