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-rw-r--r--src/Compiler.v5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/Compiler.v b/src/Compiler.v
index 80aae3f..6efd7a2 100644
--- a/src/Compiler.v
+++ b/src/Compiler.v
@@ -82,6 +82,7 @@ Qed.
Definition transf_backend (r : RTL.program) : res Verilog.program :=
OK r
+ @@@ Inlining.transf_program
@@ print (print_RTL 1)
@@@ HTLgen.transl_program
@@ print print_HTL
@@ -143,8 +144,8 @@ Proof.
exists p7; split. apply Inliningproof.transf_program_match; auto.
exists p8; split. apply HTLgenproof.transf_program_match; auto.
exists p9; split. apply Veriloggenproof.transf_program_match; auto.
- inv T. (* reflexivity. *)
-Admitted.
+ inv T. reflexivity.
+Qed.
Remark forward_simulation_identity:
forall sem, forward_simulation sem sem.