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Diffstat (limited to 'src/hls/PrintVerilog.mli')
| -rw-r--r-- | src/hls/PrintVerilog.mli | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/hls/PrintVerilog.mli b/src/hls/PrintVerilog.mli index 6a15ee9..6a996bd 100644 --- a/src/hls/PrintVerilog.mli +++ b/src/hls/PrintVerilog.mli @@ -18,8 +18,12 @@ val pprint_stmnt : int -> Verilog.stmnt -> string +val pprint_expr : Verilog.expr -> string + val print_value : out_channel -> ValueInt.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit val print_result : out_channel -> (BinNums.positive * ValueInt.value) list -> unit + +val print_io : Verilog.io option -> (string * bool) |