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-rw-r--r--src/hls/PrintVerilog.mli2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/hls/PrintVerilog.mli b/src/hls/PrintVerilog.mli
index 6a15ee9..dbb8ba0 100644
--- a/src/hls/PrintVerilog.mli
+++ b/src/hls/PrintVerilog.mli
@@ -18,6 +18,8 @@
val pprint_stmnt : int -> Verilog.stmnt -> string
+val pprint_expr : Verilog.expr -> string
+
val print_value : out_channel -> ValueInt.value -> unit
val print_program : bool -> out_channel -> Verilog.program -> unit