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-rw-r--r--src/translation/Veriloggen.v7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/translation/Veriloggen.v b/src/translation/Veriloggen.v
index f9c88bf..07034cc 100644
--- a/src/translation/Veriloggen.v
+++ b/src/translation/Veriloggen.v
@@ -30,8 +30,11 @@ Definition transl_list_fun (a : node * Verilog.stmnt) :=
Definition transl_list st := map transl_list_fun st.
-Definition scl_to_Vdecl_fun (a : reg * (option io * scl_decl)) :=
- match a with (r, (io, VScalar sz)) => (Vdecl io r sz) end.
+Definition scl_to_Vdecl_fun (a : reg * scl_decl) :=
+ match a with
+ | (r, (VScalar io sz)) => (Vdecl io r sz)
+ | (r, VWire sz) => (Vdeclwire r sz)
+ end.
Definition scl_to_Vdecl scldecl := map scl_to_Vdecl_fun scldecl.