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-rw-r--r--src/verilog/HTL.v7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v
index 82aac41..c509248 100644
--- a/src/verilog/HTL.v
+++ b/src/verilog/HTL.v
@@ -48,7 +48,12 @@ Record module: Type :=
mod_stk : reg;
mod_stk_len : nat;
mod_finish : reg;
- mod_return : reg
+ mod_return : reg;
+ mod_start : reg;
+ mod_reset : reg;
+ mod_clk : reg;
+ mod_scldecls : AssocMap.t (option Verilog.io * Verilog.scl_decl);
+ mod_arrdecls : AssocMap.t (option Verilog.io * Verilog.arr_decl);
}.
Definition fundef := AST.fundef module.