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Diffstat (limited to 'src/verilog/HTL.v')
| -rw-r--r-- | src/verilog/HTL.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index 4d0ba42..2432e7e 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -63,7 +63,7 @@ Record module: Type := mod_reset : reg; mod_clk : reg; mod_insts : AssocMap.t instantiation; - mod_scldecls : AssocMap.t (option Verilog.io * Verilog.scl_decl); + mod_scldecls : AssocMap.t Verilog.scl_decl; mod_arrdecls : AssocMap.t (option Verilog.io * Verilog.arr_decl); mod_wf : (map_well_formed mod_controllogic /\ map_well_formed mod_datapath); }. |