aboutsummaryrefslogtreecommitdiffstats
path: root/src/verilog/PrintVerilog.ml
diff options
context:
space:
mode:
Diffstat (limited to 'src/verilog/PrintVerilog.ml')
-rw-r--r--src/verilog/PrintVerilog.ml52
1 files changed, 44 insertions, 8 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml
index 04a35de..5199872 100644
--- a/src/verilog/PrintVerilog.ml
+++ b/src/verilog/PrintVerilog.ml
@@ -53,13 +53,13 @@ let unop = function
| Vneg -> " ~ "
| Vnot -> " ! "
-let register a = P.to_int a
+let register a = sprintf "reg_%d" (P.to_int a)
let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (valueToZ l))
let rec pprint_expr = function
| Vlit l -> literal l
- | Vvar s -> sprintf "reg_%d" (register s)
+ | Vvar s -> register s
| Vunop (u, e) -> concat ["("; unop u; pprint_expr e; ")"]
| Vbinop (op, a, b) -> concat ["("; pprint_expr a; pprint_binop op; pprint_expr b; ")"]
| Vternary (c, t, f) -> concat ["("; pprint_expr c; " ? "; pprint_expr t; " : "; pprint_expr f; ")"]
@@ -69,12 +69,48 @@ let rec pprint_stmnt i =
in function
| Vskip -> concat [indent i; ";\n"]
| Vseq s -> concat [indent i; "begin\n"; fold_map (pprint_stmnt (i+1)) s; indent i; "end\n"]
- | Vcond (e, st, sf) -> concat [indent i; "if ("; pprint_expr e; ")\n";
- pprint_stmnt (i + 1) st; indent i; "else\n";
- pprint_stmnt (i + 1) sf]
- | Vcase (e, es) -> concat [indent i; "case ("; pprint_expr e; ")\n";
- fold_map pprint_case es; indent i; "endcase\n"]
+ | Vcond (e, st, sf) -> concat [ indent i; "if ("; pprint_expr e; ")\n";
+ pprint_stmnt (i + 1) st; indent i; "else\n";
+ pprint_stmnt (i + 1) sf
+ ]
+ | Vcase (e, es) -> concat [ indent i; "case ("; pprint_expr e; ")\n";
+ fold_map pprint_case es; indent (i+1); "default:;\n";
+ indent i; "endcase\n"
+ ]
| Vblock (a, b) -> concat [indent i; pprint_expr a; " = "; pprint_expr b; ";\n"]
| Vnonblock (a, b) -> concat [indent i; pprint_expr a; " <= "; pprint_expr b; ";\n"]
-let print_program pp v = pstr pp (fold_map (pprint_stmnt 0) v)
+let rec pprint_edge = function
+ | Vposedge r -> concat ["posedge "; register r]
+ | Vnegedge r -> concat ["negedge "; register r]
+ | Valledge -> "*"
+ | Voredge (e1, e2) -> concat [pprint_edge e1; " or "; pprint_edge e2]
+
+let pprint_edge_top i = function
+ | Vposedge r -> concat ["@(posedge "; register r; ")"]
+ | Vnegedge r -> concat ["@(negedge "; register r; ")"]
+ | Valledge -> "@*"
+ | Voredge (e1, e2) -> concat ["@("; pprint_edge e1; " or "; pprint_edge e2; ")"]
+
+let pprint_module_item i = function
+ | Vdecl (r, n, e) ->
+ concat [indent i; "reg ["; sprintf "%d" (Nat.to_int n - 1); ":0] "; register r; " = "; pprint_expr e; ";\n"]
+ | Valways (e, s) ->
+ concat [indent i; "always "; pprint_edge_top i e; "\n"; pprint_stmnt (i+1) s]
+
+let rec intersperse c = function
+ | [] -> []
+ | [x] -> [x]
+ | x :: xs -> x :: c :: intersperse c xs
+
+let make_io i io r = concat [indent i; io; " "; register r; ";\n"]
+
+let pprint_module i n m =
+ let inputs = m.mod_start :: m.mod_reset :: m.mod_clk :: m.mod_args in
+ let outputs = [m.mod_finish; m.mod_return] in
+ concat [ indent i; "module "; n; "("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n";
+ fold_map (make_io (i+1) "input") inputs; fold_map (make_io (i+1) "output") outputs;
+ fold_map (pprint_module_item (i+1)) m.mod_body; indent i; "endmodule\n"
+ ]
+
+let print_program pp v = pstr pp (pprint_module 0 "main" v)