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-rw-r--r--src/verilog/PrintVerilog.ml3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml
index 700b8e3..a0f3ab3 100644
--- a/src/verilog/PrintVerilog.ml
+++ b/src/verilog/PrintVerilog.ml
@@ -58,7 +58,8 @@ let pprint_binop l r =
| Vor -> unsigned "|"
| Vxor -> unsigned "^"
| Vshl -> unsigned "<<"
- | Vshr -> unsigned ">>"
+ | Vshr -> signed ">>>"
+ | Vshru -> unsigned ">>"
let unop = function
| Vneg -> " ~ "