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-rw-r--r--src/verilog/PrintVerilog.ml1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml
index da4dd5d..a2fd78f 100644
--- a/src/verilog/PrintVerilog.ml
+++ b/src/verilog/PrintVerilog.ml
@@ -148,6 +148,7 @@ let print_io = function
let decl i = function
| Vdecl (io, r, sz) -> concat [indent i; declare (print_io io) (r, sz)]
| Vdeclarr (io, r, sz, ln) -> concat [indent i; declarearr (print_io io) (r, sz, ln)]
+ | Vinstancedecl inst -> concat [indent i; pprint_instantiation inst]
(* TODO Fix always blocks, as they currently always print the same. *)
let pprint_module_item i = function