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-rw-r--r--src/verilog/PrintVerilog.ml6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml
index 016a626..04a35de 100644
--- a/src/verilog/PrintVerilog.ml
+++ b/src/verilog/PrintVerilog.ml
@@ -49,6 +49,10 @@ let pprint_binop = function
| Vshl -> " << "
| Vshr -> " >> "
+let unop = function
+ | Vneg -> " ~ "
+ | Vnot -> " ! "
+
let register a = P.to_int a
let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (valueToZ l))
@@ -56,7 +60,7 @@ let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (valueToZ l))
let rec pprint_expr = function
| Vlit l -> literal l
| Vvar s -> sprintf "reg_%d" (register s)
- | Vunop e -> concat ["(~"; pprint_expr e; ")"]
+ | Vunop (u, e) -> concat ["("; unop u; pprint_expr e; ")"]
| Vbinop (op, a, b) -> concat ["("; pprint_expr a; pprint_binop op; pprint_expr b; ")"]
| Vternary (c, t, f) -> concat ["("; pprint_expr c; " ? "; pprint_expr t; " : "; pprint_expr f; ")"]