diff options
Diffstat (limited to 'src/verilog/Verilog.v')
| -rw-r--r-- | src/verilog/Verilog.v | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index 4f5c838..6f65fdc 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -177,9 +177,6 @@ Inductive stmnt : Type := | Vblock : expr -> expr -> stmnt | Vnonblock : expr -> expr -> stmnt. -Inductive instantiation : Type := - Vinstantiation : ident -> ident -> list reg -> instantiation. - (** ** Edges These define when an always block should be triggered, for example if the always @@ -209,7 +206,7 @@ Inductive io : Type := Inductive declaration : Type := | Vdecl : option io -> reg -> nat -> declaration | Vdeclarr : option io -> reg -> nat -> nat -> declaration -| Vinstancedecl : instantiation -> declaration. +| Vinstancedecl : ident -> ident -> list reg -> declaration. Inductive module_item : Type := | Vdeclaration : declaration -> module_item |