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-rw-r--r--src/verilog/Verilog.v3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v
index 8847615..4f5c838 100644
--- a/src/verilog/Verilog.v
+++ b/src/verilog/Verilog.v
@@ -208,7 +208,8 @@ Inductive io : Type :=
Inductive declaration : Type :=
| Vdecl : option io -> reg -> nat -> declaration
-| Vdeclarr : option io -> reg -> nat -> nat -> declaration.
+| Vdeclarr : option io -> reg -> nat -> nat -> declaration
+| Vinstancedecl : instantiation -> declaration.
Inductive module_item : Type :=
| Vdeclaration : declaration -> module_item