diff options
Diffstat (limited to 'src/verilog')
-rw-r--r-- | src/verilog/PrintVerilog.ml | 6 | ||||
-rw-r--r-- | src/verilog/PrintVerilog.mli | 4 |
2 files changed, 6 insertions, 4 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index f348ee6..0f64066 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -17,7 +17,7 @@ *) open Verilog -open Value +open ValueInt open Datatypes open Camlcoq @@ -70,7 +70,9 @@ let unop = function let register a = sprintf "reg_%d" (P.to_int a) -let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l)) +(*let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l))*) + +let literal l = sprintf "32'd%ld" (camlint_of_coqint l) let rec pprint_expr = function | Vlit l -> literal l diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 47af3ef..6a15ee9 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -18,8 +18,8 @@ val pprint_stmnt : int -> Verilog.stmnt -> string -val print_value : out_channel -> Value.value -> unit +val print_value : out_channel -> ValueInt.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit -val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit +val print_result : out_channel -> (BinNums.positive * ValueInt.value) list -> unit |