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-rw-r--r--src/Compiler.v15
-rw-r--r--src/extraction/Extraction.v1
2 files changed, 15 insertions, 1 deletions
diff --git a/src/Compiler.v b/src/Compiler.v
index 6efd7a2..7a99bdb 100644
--- a/src/Compiler.v
+++ b/src/Compiler.v
@@ -51,7 +51,9 @@ From vericert Require
Verilog
Veriloggen
Veriloggenproof
- HTLgen.
+ HTLgen
+ RTLBlock
+ RTLBlockgen.
From compcert Require Import Smallstep.
@@ -99,6 +101,17 @@ Definition transf_hls (p : Csyntax.program) : res Verilog.program :=
@@ print (print_RTL 0)
@@@ transf_backend.
+Definition transf_hls_temp (p : Csyntax.program) : res RTLBlock.program :=
+ OK p
+ @@@ SimplExpr.transl_program
+ @@@ SimplLocals.transf_program
+ @@@ Cshmgen.transl_program
+ @@@ Cminorgen.transl_program
+ @@@ Selection.sel_program
+ @@@ RTLgen.transl_program
+ @@ print (print_RTL 0)
+ @@@ RTLBlockgen.transl_program.
+
Local Open Scope linking_scope.
Definition CompCert's_passes :=
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v
index 9755125..6fc8545 100644
--- a/src/extraction/Extraction.v
+++ b/src/extraction/Extraction.v
@@ -175,6 +175,7 @@ Set Extraction AccessOpaque.
Cd "src/extraction".
Separate Extraction
Verilog.module Value.uvalueToZ vericert.Compiler.transf_hls
+ vericert.Compiler.transf_hls_temp
RTLBlockgen.transl_program RTLBlock.successors_instr
Compiler.transf_c_program Compiler.transf_cminor_program