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* | | Add Verilog semantics with new Verilog module | Yann Herklotz | 2020-04-15 | 1 | -33/+326 | |
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* | | Create Value module for bitvectors | Yann Herklotz | 2020-04-15 | 1 | -0/+217 | |
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* | Add proof about state wf | Yann Herklotz | 2020-04-08 | 1 | -40/+193 | |
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* | Add partial proof of well formed state | Yann Herklotz | 2020-04-06 | 1 | -24/+136 | |
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* | Update the readmev0.1.0 | Yann Herklotz | 2020-04-03 | 1 | -1/+47 | |
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* | Fix extraction on linux | Yann Herklotz | 2020-04-02 | 1 | -1/+1 | |
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* | Add gcc to build dependencies | Yann Herklotz | 2020-04-02 | 1 | -1/+3 | |
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* | Update compcert dependency | Yann Herklotz | 2020-04-02 | 2 | -0/+2 | |
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* | Update readme | Yann Herklotz | 2020-04-02 | 1 | -1/+1 | |
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* | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 4 | -114/+183 | |
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* | Update makefile for tests | Yann Herklotz | 2020-04-02 | 1 | -1/+4 | |
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* | Add tests | Yann Herklotz | 2020-04-02 | 4 | -0/+68 | |
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* | Complete translation from simple RTL to Verilog | Yann Herklotz | 2020-04-01 | 1 | -101/+162 | |
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* | Update compilation | Yann Herklotz | 2020-04-01 | 5 | -17/+84 | |
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* | Add necessary dependencies | Yann Herklotz | 2020-04-01 | 1 | -1/+1 | |
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* | Convert from RTL to Verilog directly | Yann Herklotz | 2020-03-31 | 3 | -21/+45 | |
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* | Add documentation and fix makefile for Compcert | Yann Herklotz | 2020-03-31 | 6 | -77/+107 | |
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* | Update .gitignore | Yann Herklotz | 2020-03-31 | 1 | -0/+4 | |
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* | Add more operators and print them | Yann Herklotz | 2020-03-31 | 3 | -41/+84 | |
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* | Fix the Makefile build | Yann Herklotz | 2020-03-31 | 2 | -6/+9 | |
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* | Use Compcert extraction | Yann Herklotz | 2020-03-31 | 1 | -2/+161 | |
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* | Fix Makefile build | Yann Herklotz | 2020-03-31 | 2 | -2/+6 | |
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* | Improve Verilog error messages | Yann Herklotz | 2020-03-31 | 2 | -2/+11 | |
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* | Fix Verilog printing | Yann Herklotz | 2020-03-31 | 2 | -33/+35 | |
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* | Remove main driver | Yann Herklotz | 2020-03-31 | 1 | -19/+0 | |
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* | Add main file and global building | Yann Herklotz | 2020-03-31 | 4 | -12/+450 | |
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* | Rename to transf_program | Yann Herklotz | 2020-03-29 | 1 | -1/+1 | |
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* | Move compiler | Yann Herklotz | 2020-03-29 | 1 | -2/+18 | |
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* | Complete conversion from HTL to Verilog | Yann Herklotz | 2020-03-29 | 1 | -8/+91 | |
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* | Change Verilog AST back to more traditional AST | Yann Herklotz | 2020-03-29 | 1 | -30/+44 | |
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* | Add Verilog generation from HTL | Yann Herklotz | 2020-03-29 | 1 | -0/+135 | |
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* | Update .gitignore | Yann Herklotz | 2020-03-29 | 2 | -1/+4 | |
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* | Remove unnecessary examples from HTL | Yann Herklotz | 2020-03-29 | 2 | -10/+5 | |
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* | Update AST and value representations | Yann Herklotz | 2020-03-29 | 1 | -213/+42 | |
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* | Update nix files with bbv dependency | Yann Herklotz | 2020-03-29 | 2 | -7/+29 | |
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* | Rename Verilog AST files | Yann Herklotz | 2020-03-29 | 3 | -0/+0 | |
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* | Update printing | Yann Herklotz | 2020-03-25 | 4 | -38/+56 | |
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* | Update dependencies | Yann Herklotz | 2020-03-25 | 2 | -16/+15 | |
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* | Remove dunes and make the build recursive | Yann Herklotz | 2020-03-25 | 4 | -13/+5 | |
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* | Create HTLgen | Yann Herklotz | 2020-03-25 | 3 | -148/+5 | |
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* | Move driver | Yann Herklotz | 2020-03-25 | 3 | -5/+4 | |
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* | Add Maps and HTL.v | Yann Herklotz | 2020-03-25 | 2 | -0/+235 | |
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* | Rename to HTL | Yann Herklotz | 2020-03-23 | 1 | -18/+28 | |
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* | Create intermediate VTL language | Yann Herklotz | 2020-03-22 | 1 | -0/+63 | |
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* | Create a new direct translation | Yann Herklotz | 2020-03-22 | 2 | -14/+125 | |
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* | Add compcert library to coquplib | Yann Herklotz | 2020-03-22 | 2 | -8/+13 | |
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* | Convert Tactics to Coquplib: export common modules | Yann Herklotz | 2020-03-20 | 1 | -1/+8 | |
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* | Lower case folders | Yann Herklotz | 2020-03-19 | 13 | -0/+0 | |
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* | Merge branch 'master' of github.com:ymherklotz/CoqUp | Yann Herklotz | 2020-03-19 | 1 | -2/+2 | |
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| * | Update envrc | Yann Herklotz | 2020-03-09 | 3 | -3/+8 | |
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