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* Icall proof progressMichalis Pardalos2021-09-131-35/+85
* Name the externctrl correctness clausesMichalis Pardalos2021-09-121-11/+18
* Guard join state with called module finishMichalis Pardalos2021-09-113-6/+14
* Progress with stackframe matching for IcallMichalis Pardalos2021-09-101-1/+8
* Prove that called module exists for IcallMichalis Pardalos2021-09-101-2/+26
* Add adi to polybench-syn benchmark-listMichalis Pardalos2021-09-081-0/+1
* Fix duplicated verilog module instantiationsMichalis Pardalos2021-09-081-75/+92
* Print declarations in HTL outputMichalis Pardalos2021-09-082-0/+18
* Fix renamer skipping ram_memMichalis Pardalos2021-09-031-1/+2
* Print control registers in HTL outputMichalis Pardalos2021-09-031-0/+13
* Print RAM in HTL outputMichalis Pardalos2021-09-031-0/+17
* Fix error in map_externctrlMichalis Pardalos2021-09-031-1/+1
* Remove double clockMichalis Pardalos2021-09-031-10/+2
* Do not apply externctrl to control registersMichalis Pardalos2021-09-031-34/+18
* Address ram in renaming passMichalis Pardalos2021-09-023-14/+39
* Put memorygen after renaming/applyexternctrlMichalis Pardalos2021-09-021-13/+14
* Use sumbool instead of option for decide_ram_wfMichalis Pardalos2021-09-013-12/+12
* Start renaming from 2, fixes wf_params checkMichalis Pardalos2021-09-011-1/+1
* Give specific reasons when ApplyExternctrl failsMichalis Pardalos2021-09-011-1/+5
* Fix control register ordering in Renaming passMichalis Pardalos2021-09-011-5/+7
* Give more specific reasons for Renaming failingMichalis Pardalos2021-09-011-1/+5
* Get top-level proof passingMichalis Pardalos2021-09-011-12/+14
* Get HTLgenproof to compile with RAM inferenceMichalis Pardalos2021-08-311-2/+9
* Get Memorygen to compile againMichalis Pardalos2021-08-311-475/+484
* Get HTLgenspec compiling with RAM inferenceMichalis Pardalos2021-08-311-2/+2
* Get HTLgen compiling with RAM inferenceMichalis Pardalos2021-08-311-9/+9
* Get Renaming compiling with RAM inferenceMichalis Pardalos2021-08-313-24/+37
* Get ApplyExternctrl compiling with RAM inferenceMichalis Pardalos2021-08-311-8/+16
* WIPMichalis Pardalos2021-08-306-140/+160
* Merge branch 'oopsla21' into sharing-mergeMichalis Pardalos2021-08-2691-1720/+8072
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| * Use main instead of top for synthesising Vericert designsYann Herklotz2021-07-241-1/+1
| * Update instructions and fix testv1.2.1Yann Herklotz2021-07-124-6/+5
| * Remove comments in docker fileYann Herklotz2021-07-121-3/+3
| * Update the artifact descriptionYann Herklotz2021-07-127-4/+204
| * Remove more OCaml files to compile successfully without admits.Yann Herklotz2021-07-115-1085/+0
| * Remove unnecessary files and proofsYann Herklotz2021-07-117-16/+19
| * Update the run-legup.sh fileYann Herklotz2021-07-111-0/+4
| * Add legup scriptYann Herklotz2021-07-114-4/+74
| * Fix the small test bench for VericertYann Herklotz2021-07-117-137/+67
| * Fix some more of the benchmarksYann Herklotz2021-07-118-49/+35
| * Add divider benchmarksYann Herklotz2021-07-1144-0/+3581
| * Fix makefiles and add a parent makefileYann Herklotz2021-07-104-3/+18
| * Fix Makefiles slightlyYann Herklotz2021-07-108-7/+12
| * Add more documentation and clean up benchmarksYann Herklotz2021-07-1012-158/+139
| * Add docker file and some commentsYann Herklotz2021-07-092-0/+6
| * Clean up Memorygen fileYann Herklotz2021-04-071-219/+1
| * Remove Admitted in the highest of top-levelsv1.2.0Yann Herklotz2021-04-071-5/+10
| * No admitted theorems in Memorygen proof (~‾▿‾)~Yann Herklotz2021-04-071-76/+99
| * Basically done with proofYann Herklotz2021-04-076-18/+62
| * Let everything compile againYann Herklotz2021-04-061-7/+18