| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | Add RAM semantics to HTL and fix proof | Yann Herklotz | 2021-03-03 | 4 | -18/+132 | |
| * | Add implementation | Yann Herklotz | 2021-03-02 | 2 | -29/+80 | |
| * | Add option to turn on/off ram inferrence | Yann Herklotz | 2021-03-02 | 5 | -3/+12 | |
| * | Add RAM to HTL | Yann Herklotz | 2021-03-02 | 4 | -1/+4 | |
| * | Fix memory generation by generating a power of 2 | Yann Herklotz | 2021-03-02 | 1 | -34/+50 | |
| * | Print Verilog in reverse order | Yann Herklotz | 2021-03-02 | 1 | -1/+1 | |
| * | Add Verilog generation for rams | Yann Herklotz | 2021-03-02 | 1 | -18/+47 | |
| * | Admit Veriloggenproof | Yann Herklotz | 2021-03-02 | 1 | -2/+3 | |
| * | Finish initial implementation of memory gen | Yann Herklotz | 2021-03-01 | 2 | -2/+89 | |
| * | Change lists in case statements to stmnt_list | Yann Herklotz | 2021-03-01 | 6 | -12/+30 | |
| * | Add initial memory generation | Yann Herklotz | 2021-03-01 | 1 | -0/+17 | |
| * | Fix benchmark run for master | Yann Herklotz | 2021-03-01 | 1 | -2/+2 | |
| * | Fix printing of the final cycle count | Yann Herklotz | 2021-02-21 | 1 | -2/+15 | |
| * | Fix bug in schedule | Yann Herklotz | 2021-02-19 | 1 | -2/+1 | |
| * | Fix schedule for now | Yann Herklotz | 2021-02-18 | 1 | -1/+2 | |
| * | Add udiv and sdiv to constraints | Yann Herklotz | 2021-02-17 | 1 | -12/+20 | |
| * | Remove dead code and add more constraints | Yann Herklotz | 2021-02-17 | 1 | -107/+16 | |
| * | Add option to turn off if-conversion | Yann Herklotz | 2021-02-16 | 7 | -6/+33 | |
| * | Merge branch 'master' into develop | Yann Herklotz | 2021-02-16 | 5 | -12/+623 | |
| |\ | ||||||
| | * | Remove the documentation stages | Yann Herklotz | 2021-02-16 | 1 | -8/+0 | |
| | * | Pin nixpkgs | Yann Herklotz | 2021-02-16 | 1 | -2/+1 | |
| | * | Use dune_2 instead | Yann Herklotz | 2021-02-16 | 1 | -1/+1 | |
| | * | Remove dependency on Tactics | Yann Herklotz | 2021-02-16 | 1 | -1/+0 | |
| | * | Add functional units and Sat | Yann Herklotz | 2021-02-16 | 2 | -0/+621 | |
| * | | Use topological sort for now | Yann Herklotz | 2021-02-16 | 1 | -4/+9 | |
| * | | Add schedule for new RTLPar type | Yann Herklotz | 2021-02-16 | 1 | -29/+42 | |
| * | | Fix RTLPar to use instr list list list | Yann Herklotz | 2021-02-16 | 3 | -25/+33 | |
| * | | Replace original gather function with new constraints | Yann Herklotz | 2021-02-15 | 1 | -15/+16 | |
| * | | Add resource constraints | Yann Herklotz | 2021-02-15 | 1 | -6/+71 | |
| * | | Add information about pipeline and comb_delay | Yann Herklotz | 2021-02-15 | 1 | -8/+41 | |
| * | | Add data and control dependencies to reworked graph | Yann Herklotz | 2021-02-15 | 1 | -43/+236 | |
| * | | Make the schedule a bit neater | Yann Herklotz | 2021-02-15 | 1 | -74/+63 | |
| * | | Use proper graph for DFG | Yann Herklotz | 2021-02-15 | 1 | -77/+113 | |
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| * | Add more legible names to variables | Yann Herklotz | 2021-02-12 | 1 | -1/+17 | |
| * | Add signed and unsigned division | Yann Herklotz | 2021-02-12 | 2 | -0/+339 | |
| * | Add temporary fixes to get everything to compile | Yann Herklotz | 2021-02-12 | 9 | -45/+514 | |
| * | Fix state generation for if-conversion | Yann Herklotz | 2021-02-03 | 4 | -14/+21 | |
| * | Fix scheduling for if-conversion | Yann Herklotz | 2021-02-03 | 1 | -14/+90 | |
| * | Add predicated values and instructions | Yann Herklotz | 2021-02-02 | 7 | -41/+92 | |
| * | Add if conversion pass | Yann Herklotz | 2021-02-02 | 1 | -3/+65 | |
| * | Add if conversion pass | Yann Herklotz | 2021-02-02 | 1 | -0/+32 | |
| * | Add Vrange and predicates | Yann Herklotz | 2021-02-02 | 8 | -66/+95 | |
| * | Fix OCaml files for compilation | Yann Herklotz | 2021-01-31 | 4 | -92/+94 | |
| * | Fix compilation of Coq | Yann Herklotz | 2021-01-30 | 2 | -19/+48 | |
| * | Fix proofs with better defined equality | Yann Herklotz | 2021-01-30 | 2 | -31/+57 | |
| * | Fix definitions of proofs some more | Yann Herklotz | 2021-01-29 | 4 | -106/+162 | |
| * | Fix the proof for RTLPargen | Yann Herklotz | 2021-01-29 | 1 | -32/+33 | |
| * | Fix HTLPargen and RTLPargen | Yann Herklotz | 2021-01-29 | 2 | -56/+178 | |
| * | Refactoring RTLBlock and RTLPar | Yann Herklotz | 2021-01-29 | 3 | -297/+205 | |
| * | Finish all proofs except executing basic blocks | Yann Herklotz | 2021-01-27 | 1 | -1/+4 | |
 |
index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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