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* Update default.nix filedev/full-nix-buildYann Herklotz2022-03-033-15/+4
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* Fix AbstrYann Herklotz2022-03-031-30/+17
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* Remove CompCert from gitmodulesYann Herklotz2022-03-025-34/+58
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* Update Coq version to 8.14.1Yann Herklotz2022-03-027-86/+65
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* Rename IP using systemverilog extensionYann Herklotz2022-02-283-0/+0
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* Update .gitignoreYann Herklotz2022-02-281-66/+8
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* Add ptsets.ml library from CompCert for BourdoncleYann Herklotz2022-02-282-0/+791
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* Remove .envrc as it should be localYann Herklotz2022-02-271-1/+0
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* Update documentation linksYann Herklotz2022-02-274-11/+25
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* Update documentation generationYann Herklotz2022-02-2710-6/+1336
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* Final updates to the current documentationYann Herklotz2022-02-253-18/+18
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* Fix up some more documentationYann Herklotz2022-02-257-146/+68
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* Start converting commentsYann Herklotz2022-02-253-85/+45
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* Add more documentation and add coqdoc stylesheetYann Herklotz2022-02-256-3/+928
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* Add back pure documentationYann Herklotz2022-02-255-0/+1102
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* Delete docs submoduleYann Herklotz2022-02-242-3/+0
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* Update gather data scriptYann Herklotz2022-02-231-25/+24
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* Add PrintLoops for bourdoncle codeYann Herklotz2021-12-091-0/+22
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* Update the documentationYann Herklotz2021-12-091-0/+0
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* Add bourdoncle to buildYann Herklotz2021-12-098-28/+64
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* Remove debug directoryYann Herklotz2021-12-092-64/+0
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* Update benchmark runsYann Herklotz2021-12-092-34/+80
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* Update README with correct linkYann Herklotz2021-12-092-6/+5
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* Add README.mdYann Herklotz2021-12-091-0/+147
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* Add a script to gather synthesis dataYann Herklotz2021-11-181-0/+66
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* Add a printer for RTLParFUYann Herklotz2021-11-181-0/+120
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* Fix operation chaining in schedulerYann Herklotz2021-11-181-8/+12
| | | | It now respects the delays properly.
* Remove unnecessary proof from RTLParFUgenYann Herklotz2021-11-181-1/+0
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* Fix the pipelining link in the READMEYann Herklotz2021-11-181-1/+2
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* Improve the benchmark MakefileYann Herklotz2021-11-182-4/+8
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* Fix compilation with new HTL languageYann Herklotz2021-11-1812-161/+163
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* Add bourdoncle codeYann Herklotz2021-11-184-0/+304
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* Rename pipeliningYann Herklotz2021-11-1813-0/+0
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* Fix generation of RTLParFUYann Herklotz2021-11-177-46/+30
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* Merge remote-tracking branch 'origin/dev/divider' into dev/schedulingYann Herklotz2021-11-1611-73/+353
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| * Get some Verilog output with dividersdev/dividerYann Herklotz2021-02-222-11/+22
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| * Fix Scheduling to add missing statesYann Herklotz2021-02-221-14/+34
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| * Fix arguments to RBassign and pipedYann Herklotz2021-02-224-5/+10
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| * Add operation pipeliningYann Herklotz2021-02-222-8/+137
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| * Add RTLPar printingYann Herklotz2021-02-225-4/+84
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| * Add operator pipelining passYann Herklotz2021-02-211-0/+67
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| * Add new instructions for pipelinesYann Herklotz2021-02-219-24/+33
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| * Correctly add initial scheduling variablesYann Herklotz2021-02-211-4/+20
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| * Merge branch 'develop' into dev/dividerYann Herklotz2021-02-2116-276/+1187
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| * | Add beginning to scheduling divisionYann Herklotz2021-02-157-310/+181
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* | | Finish generation of RTLParFU with RAM insertionYann Herklotz2021-11-151-24/+92
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* | | Fix max funtion in RTLParFUYann Herklotz2021-11-151-1/+2
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* | | Fix HTL generation from RTLParFUYann Herklotz2021-11-151-11/+34
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* | | Use new RAM defined in FunctionalUnits.vYann Herklotz2021-11-152-2/+4
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* | | Remove unnecessary RAMYann Herklotz2021-11-151-16/+1
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