Commit message (Expand) | Author | Age | Files | Lines | |
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* | Fix second part of proof again | Yann Herklotz | 2021-03-22 | 1 | -18/+43 |
* | Finish unchanged proof without admits | Yann Herklotz | 2021-03-22 | 1 | -21/+175 |
* | Finish a merging proof | Yann Herklotz | 2021-03-21 | 1 | -12/+30 |
* | Add many lemmas about arrays | Yann Herklotz | 2021-03-21 | 2 | -29/+250 |
* | Add check for ram in module | Yann Herklotz | 2021-03-20 | 1 | -16/+161 |
* | Prove very top-level theorem | Yann Herklotz | 2021-03-19 | 2 | -83/+176 |
* | Fix proof with new array matching | Yann Herklotz | 2021-03-17 | 1 | -20/+47 |
* | Fix main proofs with smaller admits | Yann Herklotz | 2021-03-17 | 1 | -25/+50 |
* | Proof of equivalent stmnt runs with matching start | Yann Herklotz | 2021-03-17 | 1 | -155/+263 |
* | Prove one case of transf_code correct | Yann Herklotz | 2021-03-16 | 1 | -1/+54 |
* | Greatly simplify proof | Yann Herklotz | 2021-03-16 | 1 | -44/+23 |
* | Finish proof of simple transformation | Yann Herklotz | 2021-03-16 | 1 | -0/+90 |
* | Fix memory inferrence generation | Yann Herklotz | 2021-03-15 | 1 | -28/+32 |
* | Move implicit args | Yann Herklotz | 2021-03-15 | 1 | -2/+2 |
* | Fix Verilog imports | Yann Herklotz | 2021-03-14 | 1 | -14/+20 |
* | Remove comments in Verilog.v | Yann Herklotz | 2021-03-14 | 1 | -194/+0 |
* | Prove top-level theorem with admitted theorems | Yann Herklotz | 2021-03-12 | 2 | -159/+193 |
* | Try and fix identity proof in Memorygen | Yann Herklotz | 2021-03-12 | 1 | -1/+12 |
* | Prove idempotency of array merge | Yann Herklotz | 2021-03-11 | 2 | -20/+86 |
* | Update RAM generation proofs | Yann Herklotz | 2021-03-09 | 3 | -70/+472 |
* | Add negative edge reasoning to HTLgenproof | Yann Herklotz | 2021-03-09 | 2 | -12/+109 |
* | Add RAM semantics to HTL and fix proof | Yann Herklotz | 2021-03-03 | 4 | -18/+132 |
* | Add implementation | Yann Herklotz | 2021-03-02 | 2 | -29/+80 |
* | Add option to turn on/off ram inferrence | Yann Herklotz | 2021-03-02 | 5 | -3/+12 |
* | Add RAM to HTL | Yann Herklotz | 2021-03-02 | 4 | -1/+4 |
* | Fix memory generation by generating a power of 2 | Yann Herklotz | 2021-03-02 | 1 | -34/+50 |
* | Print Verilog in reverse order | Yann Herklotz | 2021-03-02 | 1 | -1/+1 |
* | Add Verilog generation for rams | Yann Herklotz | 2021-03-02 | 1 | -18/+47 |
* | Admit Veriloggenproof | Yann Herklotz | 2021-03-02 | 1 | -2/+3 |
* | Finish initial implementation of memory gen | Yann Herklotz | 2021-03-01 | 2 | -2/+89 |
* | Change lists in case statements to stmnt_list | Yann Herklotz | 2021-03-01 | 6 | -12/+30 |
* | Add initial memory generation | Yann Herklotz | 2021-03-01 | 1 | -0/+17 |
* | Fix benchmark run for master | Yann Herklotz | 2021-03-01 | 1 | -2/+2 |
* | Fix printing of the final cycle count | Yann Herklotz | 2021-02-21 | 1 | -2/+15 |
* | Fix bug in schedule | Yann Herklotz | 2021-02-19 | 1 | -2/+1 |
* | Fix schedule for now | Yann Herklotz | 2021-02-18 | 1 | -1/+2 |
* | Add udiv and sdiv to constraints | Yann Herklotz | 2021-02-17 | 1 | -12/+20 |
* | Remove dead code and add more constraints | Yann Herklotz | 2021-02-17 | 1 | -107/+16 |
* | Add option to turn off if-conversion | Yann Herklotz | 2021-02-16 | 7 | -6/+33 |
* | Merge branch 'master' into develop | Yann Herklotz | 2021-02-16 | 5 | -12/+623 |
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| * | Remove the documentation stages | Yann Herklotz | 2021-02-16 | 1 | -8/+0 |
| * | Pin nixpkgs | Yann Herklotz | 2021-02-16 | 1 | -2/+1 |
| * | Use dune_2 instead | Yann Herklotz | 2021-02-16 | 1 | -1/+1 |
| * | Remove dependency on Tactics | Yann Herklotz | 2021-02-16 | 1 | -1/+0 |
| * | Add functional units and Sat | Yann Herklotz | 2021-02-16 | 2 | -0/+621 |
* | | Use topological sort for now | Yann Herklotz | 2021-02-16 | 1 | -4/+9 |
* | | Add schedule for new RTLPar type | Yann Herklotz | 2021-02-16 | 1 | -29/+42 |
* | | Fix RTLPar to use instr list list list | Yann Herklotz | 2021-02-16 | 3 | -25/+33 |
* | | Replace original gather function with new constraints | Yann Herklotz | 2021-02-15 | 1 | -15/+16 |
* | | Add resource constraints | Yann Herklotz | 2021-02-15 | 1 | -6/+71 |