Commit message (Expand) | Author | Age | Files | Lines | |
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* | Make top-level theorems pass | Yann Herklotz | 2021-02-16 | 1 | -4/+4 |
* | Merge branch 'michalis' of https://github.com/mpardalos/vericert into michali... | Yann Herklotz | 2021-02-16 | 1 | -9/+10 |
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| * | Implement renumbering (wrong) | Michalis Pardalos | 2021-01-25 | 1 | -8/+12 |
| * | Get top-level proofs passing. | Michalis Pardalos | 2020-12-01 | 1 | -28/+26 |
| * | Add a call instruction to HTL. Use it for Icall. | Michalis Pardalos | 2020-11-30 | 1 | -28/+28 |
| * | Revert changes relating to instance generation | Michalis Pardalos | 2020-11-27 | 1 | -2/+3 |
| * | Generate (invalid) module instantiations for calls | Michalis Pardalos | 2020-11-20 | 1 | -3/+2 |
* | | Add predicated values and instructions | Yann Herklotz | 2021-02-02 | 1 | -2/+5 |
* | | Add Vrange and predicates | Yann Herklotz | 2021-02-02 | 1 | -2/+0 |
* | | Fix imports in Coq modules | Yann Herklotz | 2021-01-21 | 1 | -43/+33 |
* | | Add missing modules to extraction and compile | Yann Herklotz | 2021-01-13 | 1 | -2/+4 |
* | | Add extraction and loop pipelining stage | Yann Herklotz | 2020-12-17 | 1 | -1/+4 |
* | | Update Compiler proof with all optimisations | Yann Herklotz | 2020-11-28 | 1 | -39/+72 |
* | | Update documentation for Compiler.v | Yann Herklotz | 2020-11-26 | 1 | -0/+84 |
* | | Add optimisations to output | Yann Herklotz | 2020-11-02 | 1 | -15/+73 |
* | | Add printing of intermediate rtlblock language | Yann Herklotz | 2020-10-23 | 1 | -1/+5 |
* | | Finish implementing scheduling and add top level export | Yann Herklotz | 2020-10-20 | 1 | -3/+7 |
* | | Add renumbering to compiler passes | Yann Herklotz | 2020-10-18 | 1 | -0/+1 |
* | | Add fixes to run scheduling on compilation | Yann Herklotz | 2020-09-03 | 1 | -1/+14 |
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* | Remove check mpass | Yann Herklotz | 2020-07-24 | 1 | -2/+0 |
* | Change name to Vericert | Yann Herklotz | 2020-07-14 | 1 | -3/+3 |
* | Fixes to operators | Yann Herklotz | 2020-07-07 | 1 | -0/+2 |
* | Rename asm to verilog | Yann Herklotz | 2020-07-06 | 1 | -9/+10 |
* | Add top level backward simulation | Yann Herklotz | 2020-07-06 | 1 | -15/+112 |
* | HTLgenproof compiles again | Yann Herklotz | 2020-07-06 | 1 | -1/+6 |
* | Add htl pretty printing | Yann Herklotz | 2020-06-30 | 1 | -0/+2 |
* | Fix top level invocation to translate through HTL | Yann Herklotz | 2020-06-12 | 1 | -3/+6 |
* | Add equality check for value | Yann Herklotz | 2020-05-04 | 1 | -1/+1 |
* | Extract simulator | Yann Herklotz | 2020-04-17 | 1 | -2/+2 |
* | Update compilation | Yann Herklotz | 2020-04-01 | 1 | -2/+2 |
* | Convert from RTL to Verilog directly | Yann Herklotz | 2020-03-31 | 1 | -3/+22 |
* | Move compiler | Yann Herklotz | 2020-03-29 | 1 | -0/+113 |