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* Put memorygen after renaming/applyexternctrlMichalis Pardalos2021-09-021-13/+14
* Get top-level proof passingMichalis Pardalos2021-09-011-12/+14
* Merge branch 'oopsla21' into sharing-mergeMichalis Pardalos2021-08-261-7/+15
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| * Remove unnecessary files and proofsYann Herklotz2021-07-111-2/+2
| * Add docker file and some commentsYann Herklotz2021-07-091-0/+2
| * Remove Admitted in the highest of top-levelsv1.2.0Yann Herklotz2021-04-071-5/+10
| * Add option to turn on/off ram inferrenceYann Herklotz2021-03-021-2/+4
* | Remove all Admitted from top-level Compiler.vMichalis Pardalos2021-06-101-35/+20
* | Get top-level (Compiler) proof closer to QedMichalis Pardalos2021-06-081-3/+27
* | Make externctrl application its own HTL passMichalis Pardalos2021-06-061-1/+4
* | Move HTL renaming pass to own fileMichalis Pardalos2021-06-061-1/+2
* | Move renumbering to be HTL->HTLMichalis Pardalos2021-04-201-3/+5
* | Merge remote-tracking branch 'upstream/master' into dev-michalisMichalis Pardalos2021-03-291-1/+2
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| * Add option to turn off if-conversionYann Herklotz2021-02-161-1/+2
* | Make top-level theorems passYann Herklotz2021-02-161-4/+4
* | Merge branch 'michalis' of https://github.com/mpardalos/vericert into michali...Yann Herklotz2021-02-161-9/+10
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| * Implement renumbering (wrong)Michalis Pardalos2021-01-251-8/+12
| * Get top-level proofs passing.Michalis Pardalos2020-12-011-28/+26
| * Add a call instruction to HTL. Use it for Icall.Michalis Pardalos2020-11-301-28/+28
| * Revert changes relating to instance generationMichalis Pardalos2020-11-271-2/+3
| * Generate (invalid) module instantiations for callsMichalis Pardalos2020-11-201-3/+2
* | Add predicated values and instructionsYann Herklotz2021-02-021-2/+5
* | Add Vrange and predicatesYann Herklotz2021-02-021-2/+0
* | Fix imports in Coq modulesYann Herklotz2021-01-211-43/+33
* | Add missing modules to extraction and compileYann Herklotz2021-01-131-2/+4
* | Add extraction and loop pipelining stageYann Herklotz2020-12-171-1/+4
* | Update Compiler proof with all optimisationsYann Herklotz2020-11-281-39/+72
* | Update documentation for Compiler.vYann Herklotz2020-11-261-0/+84
* | Add optimisations to outputYann Herklotz2020-11-021-15/+73
* | Add printing of intermediate rtlblock languageYann Herklotz2020-10-231-1/+5
* | Finish implementing scheduling and add top level exportYann Herklotz2020-10-201-3/+7
* | Add renumbering to compiler passesYann Herklotz2020-10-181-0/+1
* | Add fixes to run scheduling on compilationYann Herklotz2020-09-031-1/+14
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* Remove check mpassYann Herklotz2020-07-241-2/+0
* Change name to VericertYann Herklotz2020-07-141-3/+3
* Fixes to operatorsYann Herklotz2020-07-071-0/+2
* Rename asm to verilogYann Herklotz2020-07-061-9/+10
* Add top level backward simulationYann Herklotz2020-07-061-15/+112
* HTLgenproof compiles againYann Herklotz2020-07-061-1/+6
* Add htl pretty printingYann Herklotz2020-06-301-0/+2
* Fix top level invocation to translate through HTLYann Herklotz2020-06-121-3/+6
* Add equality check for valueYann Herklotz2020-05-041-1/+1
* Extract simulatorYann Herklotz2020-04-171-2/+2
* Update compilationYann Herklotz2020-04-011-2/+2
* Convert from RTL to Verilog directlyYann Herklotz2020-03-311-3/+22
* Move compilerYann Herklotz2020-03-291-0/+113