| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Inlined modules are valid verilog, use correct clk | Michalis Pardalos | 2021-01-26 | 1 | -0/+9 |
| * | Rename to Vericertlib | Yann Herklotz | 2020-07-17 | 1 | -0/+237 |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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