Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Add RTLPar printing | Yann Herklotz | 2021-02-22 | 1 | -0/+1 |
* | Add option to turn off if-conversion | Yann Herklotz | 2021-02-16 | 1 | -1/+5 |
* | Add temporary fixes to get everything to compile | Yann Herklotz | 2021-02-12 | 1 | -0/+1 |
* | Fix compilation of Coq | Yann Herklotz | 2021-01-30 | 1 | -1/+3 |
* | Add missing modules to extraction and compile | Yann Herklotz | 2021-01-13 | 1 | -2/+1 |
* | Add extraction and loop pipelining stage | Yann Herklotz | 2020-12-17 | 1 | -2/+4 |
* | Fix build for Coq 8.12.1 | Yann Herklotz | 2020-11-26 | 1 | -2/+1 |
* | Add optimisations to output | Yann Herklotz | 2020-11-02 | 1 | -0/+1 |
* | Add tbl_to_casestatement into extraction | Yann Herklotz | 2020-10-26 | 1 | -1/+3 |
* | Add printing of intermediate rtlblock language | Yann Herklotz | 2020-10-23 | 1 | -0/+1 |
* | Finish implementing scheduling and add top level export | Yann Herklotz | 2020-10-20 | 1 | -1/+3 |
* | Add fixes to run scheduling on compilation | Yann Herklotz | 2020-09-03 | 1 | -0/+1 |
* | Continue on Partitioning algorithm | Yann Herklotz | 2020-08-30 | 1 | -2/+3 |
* | Add RTLBlock intermediate language | Yann Herklotz | 2020-08-30 | 1 | -1/+8 |
* | Change name to Vericert | Yann Herklotz | 2020-07-14 | 1 | -4/+4 |
* | Add htl pretty printing | Yann Herklotz | 2020-06-30 | 1 | -0/+1 |
* | Remove extraction of simulator | Yann Herklotz | 2020-06-12 | 1 | -2/+2 |
* | Add equality check for value | Yann Herklotz | 2020-05-04 | 1 | -1/+1 |
* | Extract simulator | Yann Herklotz | 2020-04-17 | 1 | -3/+3 |
* | Fix extraction on linux | Yann Herklotz | 2020-04-02 | 1 | -1/+1 |
* | Update compilation | Yann Herklotz | 2020-04-01 | 1 | -1/+1 |
* | Convert from RTL to Verilog directly | Yann Herklotz | 2020-03-31 | 1 | -0/+3 |
* | Use Compcert extraction | Yann Herklotz | 2020-03-31 | 1 | -2/+161 |
* | Lower case folders | Yann Herklotz | 2020-03-19 | 1 | -0/+30 |