Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Work more on equivalence of SAT | Yann Herklotz | 2021-10-26 | 1 | -1/+1 |
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* | Fix pretty printing issue in Verilog | Yann Herklotz | 2021-08-12 | 1 | -1/+1 |
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* | Fix initialisation more | Yann Herklotz | 2021-04-01 | 1 | -7/+7 |
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* | Add 0 initialisation | Yann Herklotz | 2021-04-01 | 1 | -1/+1 |
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* | Add new enable interface | Yann Herklotz | 2021-04-01 | 1 | -3/+3 |
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* | Add memory disable | Yann Herklotz | 2021-03-31 | 1 | -3/+6 |
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* | Print Verilog in reverse order | Yann Herklotz | 2021-03-02 | 1 | -1/+1 |
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* | Change lists in case statements to stmnt_list | Yann Herklotz | 2021-03-01 | 1 | -1/+3 |
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* | Fix printing of the final cycle count | Yann Herklotz | 2021-02-21 | 1 | -2/+15 |
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* | Add more legible names to variables | Yann Herklotz | 2021-02-12 | 1 | -1/+17 |
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* | Fix state generation for if-conversion | Yann Herklotz | 2021-02-03 | 1 | -3/+9 |
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* | Add predicated values and instructions | Yann Herklotz | 2021-02-02 | 1 | -0/+1 |
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* | Add correct copyright notices in files | Yann Herklotz | 2021-01-10 | 1 | -0/+1 |
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* | Fix pretty printing bug in Verilog | Yann Herklotz | 2020-11-02 | 1 | -2/+2 |
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* | Fix printing of negative numbers | Yann Herklotz | 2020-10-23 | 1 | -1/+5 |
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* | Add RTLBlock intermediate language | Yann Herklotz | 2020-08-30 | 1 | -0/+232 |