| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix renamer skipping ram_mem | Michalis Pardalos | 2021-09-03 | 1 | -1/+2 |
| | | |||||
| * | Address ram in renaming pass | Michalis Pardalos | 2021-09-02 | 1 | -2/+20 |
| | | |||||
| * | Use sumbool instead of option for decide_ram_wf | Michalis Pardalos | 2021-09-01 | 1 | -3/+3 |
| | | |||||
| * | Start renaming from 2, fixes wf_params check | Michalis Pardalos | 2021-09-01 | 1 | -1/+1 |
| | | |||||
| * | Fix control register ordering in Renaming pass | Michalis Pardalos | 2021-09-01 | 1 | -5/+7 |
| | | |||||
| * | Give more specific reasons for Renaming failing | Michalis Pardalos | 2021-09-01 | 1 | -1/+5 |
| | | |||||
| * | Get Renaming compiling with RAM inference | Michalis Pardalos | 2021-08-31 | 1 | -10/+23 |
| | | |||||
| * | WIP | Michalis Pardalos | 2021-08-30 | 1 | -4/+4 |
| | | |||||
| * | Remove all Admitted from top-level Compiler.v | Michalis Pardalos | 2021-06-10 | 1 | -0/+13 |
| | | |||||
| * | Move HTL renaming pass to own file | Michalis Pardalos | 2021-06-06 | 1 | -0/+218 |
 |
index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
| aboutsummaryrefslogtreecommitdiffstats |