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path: root/src/hls/Verilog.v
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* Merge branch 'oopsla21' into sharing-mergeMichalis Pardalos2021-08-261-231/+195
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| * Finish load and store proof, but broke top-levelYann Herklotz2021-04-061-0/+37
| * Finish Veriloggenproof completelyYann Herklotz2021-04-041-16/+83
| * Move implicit argsYann Herklotz2021-03-151-2/+2
| * Fix Verilog importsYann Herklotz2021-03-141-14/+20
| * Remove comments in Verilog.vYann Herklotz2021-03-141-194/+0
| * Add negative edge reasoning to HTLgenproofYann Herklotz2021-03-091-0/+33
| * Change lists in case statements to stmnt_listYann Herklotz2021-03-011-7/+22
* | Merge branch 'michalis' of https://github.com/mpardalos/vericert into michali...Yann Herklotz2021-02-161-0/+14
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* Add Vrange and predicatesYann Herklotz2021-02-021-0/+2
* Add correct copyright notices in filesYann Herklotz2021-01-101-0/+1
* Update definition of VnegYann Herklotz2020-11-071-1/+1
* Add RTLBlock intermediate languageYann Herklotz2020-08-301-0/+893