| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Handle declarations of externctrl regs in Verilog | Michalis Pardalos | 2021-05-01 | 1 | -24/+41 |
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| * | Remove some dead code from Veriloggen | Michalis Pardalos | 2021-05-01 | 1 | -17/+0 |
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| * | Fix typo bug in applying externctrl | Michalis Pardalos | 2021-05-01 | 1 | -2/+2 |
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| * | Print externctrl in HTL debug output | Michalis Pardalos | 2021-05-01 | 1 | -5/+10 |
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| * | Apply externctrl mapping in HTL->Verilog stage | Michalis Pardalos | 2021-04-30 | 1 | -22/+147 |
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| * | Move renumbering to be HTL->HTL | Michalis Pardalos | 2021-04-20 | 1 | -230/+12 |
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| * | Typos in Veriloggen | Michalis Pardalos | 2021-03-01 | 1 | -2/+2 |
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| * | Unset finish signal on reset | Michalis Pardalos | 2021-02-28 | 1 | -1/+3 |
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| * | Merge branch 'michalis' of https://github.com/mpardalos/vericert into ↵ | Yann Herklotz | 2021-02-16 | 1 | -44/+339 |
| | | | | | michalis-merge | ||||
| * | Fix imports to remove warnings when compiling | Yann Herklotz | 2021-01-22 | 1 | -18/+23 |
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| * | Add RTLBlock intermediate language | Yann Herklotz | 2020-08-30 | 1 | -0/+65 |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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