| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | Fix proof with new array matching | Yann Herklotz | 2021-03-17 | 1 | -20/+47 | |
| * | | | Fix main proofs with smaller admits | Yann Herklotz | 2021-03-17 | 1 | -25/+50 | |
| * | | | Proof of equivalent stmnt runs with matching start | Yann Herklotz | 2021-03-17 | 1 | -155/+263 | |
| * | | | Prove one case of transf_code correct | Yann Herklotz | 2021-03-16 | 1 | -1/+54 | |
| * | | | Greatly simplify proof | Yann Herklotz | 2021-03-16 | 1 | -44/+23 | |
| * | | | Finish proof of simple transformation | Yann Herklotz | 2021-03-16 | 1 | -0/+90 | |
| * | | | Fix memory inferrence generation | Yann Herklotz | 2021-03-15 | 1 | -28/+32 | |
| * | | | Move implicit args | Yann Herklotz | 2021-03-15 | 1 | -2/+2 | |
| * | | | Fix Verilog imports | Yann Herklotz | 2021-03-14 | 1 | -14/+20 | |
| * | | | Remove comments in Verilog.v | Yann Herklotz | 2021-03-14 | 1 | -194/+0 | |
| * | | | Prove top-level theorem with admitted theorems | Yann Herklotz | 2021-03-12 | 2 | -159/+193 | |
| * | | | Try and fix identity proof in Memorygen | Yann Herklotz | 2021-03-12 | 1 | -1/+12 | |
| * | | | Prove idempotency of array merge | Yann Herklotz | 2021-03-11 | 2 | -20/+86 | |
| * | | | Update RAM generation proofs | Yann Herklotz | 2021-03-09 | 3 | -70/+472 | |
| * | | | Add negative edge reasoning to HTLgenproof | Yann Herklotz | 2021-03-09 | 2 | -12/+109 | |
| * | | | Add RAM semantics to HTL and fix proof | Yann Herklotz | 2021-03-03 | 4 | -18/+132 | |
| * | | | Add implementation | Yann Herklotz | 2021-03-02 | 2 | -29/+80 | |
| * | | | Add RAM to HTL | Yann Herklotz | 2021-03-02 | 4 | -1/+4 | |
| * | | | Fix memory generation by generating a power of 2 | Yann Herklotz | 2021-03-02 | 1 | -34/+50 | |
| * | | | Print Verilog in reverse order | Yann Herklotz | 2021-03-02 | 1 | -1/+1 | |
| * | | | Add Verilog generation for rams | Yann Herklotz | 2021-03-02 | 1 | -18/+47 | |
| * | | | Admit Veriloggenproof | Yann Herklotz | 2021-03-02 | 1 | -2/+3 | |
| * | | | Finish initial implementation of memory gen | Yann Herklotz | 2021-03-01 | 2 | -2/+89 | |
| * | | | Change lists in case statements to stmnt_list | Yann Herklotz | 2021-03-01 | 5 | -12/+29 | |
| * | | | Add initial memory generation | Yann Herklotz | 2021-03-01 | 1 | -0/+17 | |
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| * | | Fix printing of the final cycle count | Yann Herklotz | 2021-02-21 | 1 | -2/+15 | |
| * | | Fix bug in schedule | Yann Herklotz | 2021-02-19 | 1 | -2/+1 | |
| * | | Fix schedule for now | Yann Herklotz | 2021-02-18 | 1 | -1/+2 | |
| * | | Add udiv and sdiv to constraints | Yann Herklotz | 2021-02-17 | 1 | -12/+20 | |
| * | | Remove dead code and add more constraints | Yann Herklotz | 2021-02-17 | 1 | -107/+16 | |
| * | | Add option to turn off if-conversion | Yann Herklotz | 2021-02-16 | 1 | -2/+2 | |
| * | | Merge branch 'master' into develop | Yann Herklotz | 2021-02-16 | 2 | -0/+621 | |
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| | * | | Add functional units and Sat | Yann Herklotz | 2021-02-16 | 2 | -0/+621 | |
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| * | | Use topological sort for now | Yann Herklotz | 2021-02-16 | 1 | -4/+9 | |
| * | | Add schedule for new RTLPar type | Yann Herklotz | 2021-02-16 | 1 | -29/+42 | |
| * | | Fix RTLPar to use instr list list list | Yann Herklotz | 2021-02-16 | 3 | -25/+33 | |
| * | | Replace original gather function with new constraints | Yann Herklotz | 2021-02-15 | 1 | -15/+16 | |
| * | | Add resource constraints | Yann Herklotz | 2021-02-15 | 1 | -6/+71 | |
| * | | Add information about pipeline and comb_delay | Yann Herklotz | 2021-02-15 | 1 | -8/+41 | |
| * | | Add data and control dependencies to reworked graph | Yann Herklotz | 2021-02-15 | 1 | -43/+236 | |
| * | | Make the schedule a bit neater | Yann Herklotz | 2021-02-15 | 1 | -74/+63 | |
| * | | Use proper graph for DFG | Yann Herklotz | 2021-02-15 | 1 | -77/+113 | |
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| * | Add more legible names to variables | Yann Herklotz | 2021-02-12 | 1 | -1/+17 | |
| * | Add temporary fixes to get everything to compile | Yann Herklotz | 2021-02-12 | 6 | -36/+385 | |
| * | Fix state generation for if-conversion | Yann Herklotz | 2021-02-03 | 4 | -14/+21 | |
| * | Fix scheduling for if-conversion | Yann Herklotz | 2021-02-03 | 1 | -14/+90 | |
| * | Add predicated values and instructions | Yann Herklotz | 2021-02-02 | 6 | -39/+87 | |
| * | Add if conversion pass | Yann Herklotz | 2021-02-02 | 1 | -3/+65 | |
| * | Add if conversion pass | Yann Herklotz | 2021-02-02 | 1 | -0/+32 | |
| * | Add Vrange and predicates | Yann Herklotz | 2021-02-02 | 7 | -64/+95 | |
 |
index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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