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* Get some Verilog output with dividersdev/dividerYann Herklotz2021-02-222-11/+22
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* Fix Scheduling to add missing statesYann Herklotz2021-02-221-14/+34
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* Fix arguments to RBassign and pipedYann Herklotz2021-02-224-5/+10
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* Add operation pipeliningYann Herklotz2021-02-221-8/+133
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* Add RTLPar printingYann Herklotz2021-02-221-0/+74
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* Add operator pipelining passYann Herklotz2021-02-211-0/+67
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* Add new instructions for pipelinesYann Herklotz2021-02-219-24/+33
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* Correctly add initial scheduling variablesYann Herklotz2021-02-211-4/+20
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* Merge branch 'develop' into dev/dividerYann Herklotz2021-02-217-260/+1154
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| * Fix printing of the final cycle countYann Herklotz2021-02-211-2/+15
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| * Fix bug in scheduleYann Herklotz2021-02-191-2/+1
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| * Fix schedule for nowYann Herklotz2021-02-181-1/+2
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| * Add udiv and sdiv to constraintsYann Herklotz2021-02-171-12/+20
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| * Remove dead code and add more constraintsYann Herklotz2021-02-171-107/+16
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| * Add option to turn off if-conversionYann Herklotz2021-02-161-2/+2
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| * Merge branch 'master' into developYann Herklotz2021-02-162-0/+621
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| | * Add functional units and SatYann Herklotz2021-02-162-0/+621
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| * | Use topological sort for nowYann Herklotz2021-02-161-4/+9
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| * | Add schedule for new RTLPar typeYann Herklotz2021-02-161-29/+42
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| * | Fix RTLPar to use instr list list listYann Herklotz2021-02-163-25/+33
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| * | Replace original gather function with new constraintsYann Herklotz2021-02-151-15/+16
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| * | Add resource constraintsYann Herklotz2021-02-151-6/+71
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| * | Add information about pipeline and comb_delayYann Herklotz2021-02-151-8/+41
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| * | Add data and control dependencies to reworked graphYann Herklotz2021-02-151-43/+236
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| * | Make the schedule a bit neaterYann Herklotz2021-02-151-74/+63
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| * | Use proper graph for DFGYann Herklotz2021-02-151-77/+113
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* / Add beginning to scheduling divisionYann Herklotz2021-02-157-310/+181
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* Add more legible names to variablesYann Herklotz2021-02-121-1/+17
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* Add temporary fixes to get everything to compileYann Herklotz2021-02-126-36/+385
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* Fix state generation for if-conversionYann Herklotz2021-02-034-14/+21
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* Fix scheduling for if-conversionYann Herklotz2021-02-031-14/+90
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* Add predicated values and instructionsYann Herklotz2021-02-026-39/+87
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* Add if conversion passYann Herklotz2021-02-021-3/+65
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* Add if conversion passYann Herklotz2021-02-021-0/+32
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* Add Vrange and predicatesYann Herklotz2021-02-027-64/+95
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* Fix OCaml files for compilationYann Herklotz2021-01-314-92/+94
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* Fix compilation of CoqYann Herklotz2021-01-301-18/+45
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* Fix proofs with better defined equalityYann Herklotz2021-01-302-31/+57
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* Fix definitions of proofs some moreYann Herklotz2021-01-294-106/+162
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* Fix the proof for RTLPargenYann Herklotz2021-01-291-32/+33
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* Fix HTLPargen and RTLPargenYann Herklotz2021-01-292-56/+178
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* Refactoring RTLBlock and RTLParYann Herklotz2021-01-293-297/+205
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* Finish all proofs except executing basic blocksYann Herklotz2021-01-271-1/+4
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* Add more proofs for RTLPargen correctnessYann Herklotz2021-01-273-26/+97
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* Add basic block matching and proofYann Herklotz2021-01-261-3/+78
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* Remove the schedule oracleYann Herklotz2021-01-262-518/+515
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* Add an inductive to enter the basic blockYann Herklotz2021-01-261-3/+3
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* Use basic blocks in context to help proofYann Herklotz2021-01-261-11/+15
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* Remove match on basic blocksYann Herklotz2021-01-231-6/+0
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* Add match_states for RTLPargen proofYann Herklotz2021-01-222-4/+78
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