| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Give a (questionable) translation spec for HTLgen | Michalis Pardalos | 2021-05-02 | 2 | -39/+61 | |
| | | | | | | | | | | | I am not yet convinced it is the right one, particularly around the way I've used existentials. I will be updating it as I progress with the proof. | |||||
| * | | Simplify some HTLgenspec proofs | Michalis Pardalos | 2021-05-02 | 1 | -2/+2 | |
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| * | | Handle declarations of externctrl regs in Verilog | Michalis Pardalos | 2021-05-01 | 1 | -24/+41 | |
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| * | | Remove some dead code from Veriloggen | Michalis Pardalos | 2021-05-01 | 1 | -17/+0 | |
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| * | | Fix HTLgen using wrong register in call wait state | Michalis Pardalos | 2021-05-01 | 1 | -2/+3 | |
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| * | | Fix typo bug in applying externctrl | Michalis Pardalos | 2021-05-01 | 1 | -2/+2 | |
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| * | | Print externctrl in HTL debug output | Michalis Pardalos | 2021-05-01 | 2 | -6/+31 | |
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| * | | Apply externctrl mapping in HTL->Verilog stage | Michalis Pardalos | 2021-04-30 | 1 | -22/+147 | |
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| * | | Tie all modules' clock to main | Michalis Pardalos | 2021-04-30 | 4 | -16/+47 | |
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| * | | Fix map_externctrl double-incrementing freshreg | Michalis Pardalos | 2021-04-30 | 1 | -3/+2 | |
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| * | | Delete unused get_main_clk function from HTLgen | Michalis Pardalos | 2021-04-30 | 1 | -11/+0 | |
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| * | | Map clock correctly in RTL->HTL | Michalis Pardalos | 2021-04-29 | 1 | -15/+9 | |
| | | | | | | | | | Remove the renumber_clk param of the renumber state | |||||
| * | | Renumber AssocMaps in HTL modules too | Michalis Pardalos | 2021-04-20 | 2 | -7/+25 | |
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| * | | Move renumbering to be HTL->HTL | Michalis Pardalos | 2021-04-20 | 3 | -234/+229 | |
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| * | | Get HTLgenproof to compile | Michalis Pardalos | 2021-04-20 | 2 | -279/+280 | |
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| * | | Update HTLPargen for new HTL | Michalis Pardalos | 2021-04-20 | 1 | -30/+25 | |
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| * | | Update ocaml code match HTL changes | Michalis Pardalos | 2021-04-20 | 1 | -25/+2 | |
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| * | | [WIP] Re-implement translation of calls. | Michalis Pardalos | 2021-04-19 | 2 | -33/+84 | |
| | | | | | | | | | | | Add an explicit map of local HTL registers to control signals and params of other modules, used to implement calls. | |||||
| * | | [WIP] Use Program instead of state_incr lemmas | Michalis Pardalos | 2021-04-18 | 1 | -165/+40 | |
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| * | | [WIP] Generate calling verilog in RTL->HTL | Michalis Pardalos | 2021-04-18 | 1 | -15/+40 | |
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| * | | [WIP] Remove extra statements from HTL. | Michalis Pardalos | 2021-04-18 | 2 | -73/+18 | |
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| * | | [WIP] HTLgenspec proof | Michalis Pardalos | 2021-04-17 | 1 | -46/+34 | |
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| * | | Fix up rest of HTLgenproof | Michalis Pardalos | 2021-04-09 | 1 | -62/+46 | |
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| * | | Fix merge error in oshrximm | Michalis Pardalos | 2021-04-09 | 1 | -1/+3 | |
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| * | | Get HTLgenproof to compile | Michalis Pardalos | 2021-04-08 | 1 | -87/+89 | |
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| * | | [WIP] Add semantics for new HTL instructions | Michalis Pardalos | 2021-04-02 | 1 | -38/+72 | |
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| * | | Merge remote-tracking branch 'upstream/master' into dev-michalis | Michalis Pardalos | 2021-03-29 | 5 | -260/+533 | |
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| | * | Fix printing of the final cycle count | Yann Herklotz | 2021-02-21 | 1 | -2/+15 | |
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| | * | Fix bug in schedule | Yann Herklotz | 2021-02-19 | 1 | -2/+1 | |
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| | * | Fix schedule for now | Yann Herklotz | 2021-02-18 | 1 | -1/+2 | |
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| | * | Add udiv and sdiv to constraints | Yann Herklotz | 2021-02-17 | 1 | -12/+20 | |
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| | * | Remove dead code and add more constraints | Yann Herklotz | 2021-02-17 | 1 | -107/+16 | |
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| | * | Add option to turn off if-conversion | Yann Herklotz | 2021-02-16 | 1 | -2/+2 | |
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| | * | Merge branch 'master' into develop | Yann Herklotz | 2021-02-16 | 2 | -0/+621 | |
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| | * | | Use topological sort for now | Yann Herklotz | 2021-02-16 | 1 | -4/+9 | |
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| | * | | Add schedule for new RTLPar type | Yann Herklotz | 2021-02-16 | 1 | -29/+42 | |
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| | * | | Fix RTLPar to use instr list list list | Yann Herklotz | 2021-02-16 | 3 | -25/+33 | |
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| | * | | Replace original gather function with new constraints | Yann Herklotz | 2021-02-15 | 1 | -15/+16 | |
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| | * | | Add resource constraints | Yann Herklotz | 2021-02-15 | 1 | -6/+71 | |
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| | * | | Add information about pipeline and comb_delay | Yann Herklotz | 2021-02-15 | 1 | -8/+41 | |
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| | * | | Add data and control dependencies to reworked graph | Yann Herklotz | 2021-02-15 | 1 | -43/+236 | |
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| | * | | Make the schedule a bit neater | Yann Herklotz | 2021-02-15 | 1 | -74/+63 | |
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| | * | | Use proper graph for DFG | Yann Herklotz | 2021-02-15 | 1 | -77/+113 | |
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| * | | | Add idle state after return | Michalis Pardalos | 2021-03-01 | 2 | -33/+37 | |
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| * | | | Typos in Veriloggen | Michalis Pardalos | 2021-03-01 | 1 | -2/+2 | |
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| * | | | Unset finish signal on reset | Michalis Pardalos | 2021-02-28 | 1 | -1/+3 | |
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| * | | | Merge branch 'master' into michalis-merge | Yann Herklotz | 2021-02-16 | 2 | -0/+621 | |
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| | * | | Add functional units and Sat | Yann Herklotz | 2021-02-16 | 2 | -0/+621 | |
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| * | | Make top-level theorems pass | Yann Herklotz | 2021-02-16 | 2 | -44/+49 | |
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| * | | Add changes to HTL as they weren't merged | Yann Herklotz | 2021-02-16 | 1 | -53/+122 | |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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