| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Only generate clocked always blocks | Yann Herklotz | 2020-04-17 | 1 | -13/+13 |
| * | Make proofs simpler using auto | Yann Herklotz | 2020-04-15 | 1 | -59/+45 |
| * | Add proof about state wf | Yann Herklotz | 2020-04-08 | 1 | -40/+193 |
| * | Add partial proof of well formed state | Yann Herklotz | 2020-04-06 | 1 | -24/+136 |
| * | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 1 | -100/+128 |
| * | Complete translation from simple RTL to Verilog | Yann Herklotz | 2020-04-01 | 1 | -101/+162 |
| * | Convert from RTL to Verilog directly | Yann Herklotz | 2020-03-31 | 1 | -18/+20 |
| * | Add more operators and print them | Yann Herklotz | 2020-03-31 | 1 | -37/+69 |
| * | Improve Verilog error messages | Yann Herklotz | 2020-03-31 | 1 | -1/+7 |
| * | Rename to transf_program | Yann Herklotz | 2020-03-29 | 1 | -1/+1 |
| * | Complete conversion from HTL to Verilog | Yann Herklotz | 2020-03-29 | 1 | -8/+91 |
| * | Add Verilog generation from HTL | Yann Herklotz | 2020-03-29 | 1 | -0/+135 |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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