Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Redefine HTL for intermediate Verilog language | Yann Herklotz | 2020-05-07 | 1 | -0/+18 |
* | Add proofs and specification of Verilog conversion | Yann Herklotz | 2020-05-03 | 1 | -0/+112 |
index : vericert | ||
Vericert is a formally verified high-level synthesis tool. |
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Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Redefine HTL for intermediate Verilog language | Yann Herklotz | 2020-05-07 | 1 | -0/+18 |
* | Add proofs and specification of Verilog conversion | Yann Herklotz | 2020-05-03 | 1 | -0/+112 |