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* | Merge branch 'master' into arrays-proofJames Pollard2020-06-126-834/+205
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| * Add declaration of loadsYann Herklotz2020-06-122-4/+6
| * Fix declaring function arguments correctlyYann Herklotz2020-06-122-9/+66
| * Remove Verilog proofsYann Herklotz2020-06-122-132/+4
| * Declare all registers properly in HTLYann Herklotz2020-06-123-51/+95
| * Generate Verilog from HTLYann Herklotz2020-06-121-644/+40
* | Some work on store proof.James Pollard2020-06-121-11/+38
* | Rough outline of stack address proofJames Pollard2020-06-112-30/+105
* | Working on proof.James Pollard2020-06-113-41/+136
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* Start fixing proofJames Pollard2020-06-091-94/+116
* Fix automation tactic for modified constructorJames Pollard2020-06-091-2/+4
* Start extending HTL proof to cover arrays.James Pollard2020-06-091-18/+31
* Merge branch 'develop' into arrays-proofJames Pollard2020-06-091-31/+92
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| * Finished main proof with small assumptionsYann Herklotz2020-06-042-34/+94
* | Fix HTLgenspec proof for arrays.James Pollard2020-06-031-31/+43
* | Merge branch 'develop' into arrays-proofJames Pollard2020-06-032-47/+45
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| * Uncomment proofYann Herklotz2020-06-032-43/+41
* | HTLgenspec status in line with developJames Pollard2020-06-032-26/+56
* | Copy over load/store from Veriloggen to HTLgen.James Pollard2020-06-031-5/+36
* | Merge branch 'develop' into arrays-proofJames Pollard2020-06-032-4/+30
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| * Add proof to final_statesYann Herklotz2020-06-021-1/+3
| * Add proof for initial stateYann Herklotz2020-06-022-3/+27
* | Keep track of declarations in HTLgen.James Pollard2020-06-031-23/+62
* | Merge branch 'develop' into arrays-proofJames Pollard2020-06-023-82/+152
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| * Get whole proof to compileYann Herklotz2020-06-021-14/+17
| * Shorten the proof a bitYann Herklotz2020-06-021-41/+15
| * Add proof for equivalence of movYann Herklotz2020-06-022-38/+110
| * Add lemmas for preservation of globalsYann Herklotz2020-06-012-29/+50
* | Merge branch 'develop' into arrays-proofJames Pollard2020-06-011-5/+4
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| * Small optimisations to proofYann Herklotz2020-05-311-5/+4
* | Merge branch 'develop' into arrays-proofJames Pollard2020-05-306-162/+1327
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| * Merge branch 'develop' of github.com:ymherklotz/CoqUp into developYann Herklotz2020-05-291-6/+3
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| | * Improve automation in HTLgenspec.James Pollard2020-05-291-6/+3
| * | Fix compilation moving to PTreeYann Herklotz2020-05-293-25/+34
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| * Change AssocMap to Maps.PTreeYann Herklotz2020-05-291-3/+5
| * Add more proofs and remove AdmittedYann Herklotz2020-05-271-49/+43
| * Add top level definitionYann Herklotz2020-05-272-138/+153
| * Working on automationYann Herklotz2020-05-261-62/+48
| * Finished proof of spec completelyYann Herklotz2020-05-262-5/+94
| * Finished second pass and fixed bugYann Herklotz2020-05-262-18/+37
| * Finished proving the first caseYann Herklotz2020-05-251-1/+6
| * Continuing work on proving specificationYann Herklotz2020-05-252-22/+218
| * Add HTLgenYann Herklotz2020-05-241-1/+337
| * Finish the proof with most assumptionsYann Herklotz2020-05-212-29/+150
| * Add proof of translation correctnessYann Herklotz2020-05-202-17/+200
| * Add simulation diagramYann Herklotz2020-05-081-5/+53
| * Add match_states InductiveYann Herklotz2020-05-071-0/+29
| * Remove HTLgen and create the specificationYann Herklotz2020-05-072-163/+92
| * Redefine HTL for intermediate Verilog languageYann Herklotz2020-05-071-0/+18
| * Add equality check for valueYann Herklotz2020-05-042-2/+2
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