vericert - Vericert is a formally verified high-level synthesis tool.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Handle loops and conditionals correctly	Yann Herklotz	2020-04-02	1	-100/+128
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*	Complete translation from simple RTL to Verilog	Yann Herklotz	2020-04-01	1	-101/+162
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*	Convert from RTL to Verilog directly	Yann Herklotz	2020-03-31	1	-18/+20
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*	Add more operators and print them	Yann Herklotz	2020-03-31	1	-37/+69
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*	Improve Verilog error messages	Yann Herklotz	2020-03-31	1	-1/+7
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*	Rename to transf_program	Yann Herklotz	2020-03-29	1	-1/+1
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*	Complete conversion from HTL to Verilog	Yann Herklotz	2020-03-29	1	-8/+91
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*	Add Verilog generation from HTL	Yann Herklotz	2020-03-29	1	-0/+135
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*	Remove unnecessary examples from HTL	Yann Herklotz	2020-03-29	1	-6/+1
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*	Create HTLgen	Yann Herklotz	2020-03-25	3	-148/+5
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*	Add Maps and HTL.v	Yann Herklotz	2020-03-25	1	-0/+186
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*	Create a new direct translation	Yann Herklotz	2020-03-22	2	-14/+125
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*	Update names of directories	Yann Herklotz	2020-03-19	1	-0/+37