| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Separate HTL instantiations from Verilog ones | Michalis Pardalos | 2020-11-20 | 1 | -2/+0 |
| | | | | | | | | | | | | In HTL, they reference their data arguments, destination, and finished control signal. Meanwhile, in Verilog, they just contain an unstructured list of parameters. This is done because when modules are generated in the HTL stage we do not have access to any of the instantiating module's control signals (they are declared after the entirety of the module has been translated). Also, I believe, these signals are not part of the HTL semantics. | ||||
| * | Print instantiations in HTL output | Michalis Pardalos | 2020-11-20 | 1 | -0/+2 |
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| * | More renames to get it to compile | Yann Herklotz | 2020-07-24 | 1 | -2/+2 |
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| * | Change name to Vericert | Yann Herklotz | 2020-07-14 | 1 | -1/+1 |
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| * | Add htl pretty printing | Yann Herklotz | 2020-06-30 | 1 | -0/+2 |
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| * | Add print for debug always block in module | Yann Herklotz | 2020-06-22 | 1 | -1/+1 |
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| * | Fix printing of Verilog with new datatypes | Yann Herklotz | 2020-06-12 | 1 | -1/+1 |
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| * | Improve printing of results | Yann Herklotz | 2020-04-22 | 1 | -1/+3 |
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| * | Fix printing with new Verilog AST | Yann Herklotz | 2020-04-17 | 1 | -0/+2 |
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| * | Update compilation | Yann Herklotz | 2020-04-01 | 1 | -1/+1 |
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| * | Fix Verilog printing | Yann Herklotz | 2020-03-31 | 1 | -1/+1 |
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| * | Rename Verilog AST files | Yann Herklotz | 2020-03-29 | 1 | -0/+19 |
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index : vericert | |
| Vericert is a formally verified high-level synthesis tool. |
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